Bao Zheng would like Zheng Bao to review this change.
soc/amd/cezanne: Add PSP integration for cezanne
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/fw.cfg
3 files changed, 343 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48528/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index be45de4..885afb3 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -98,4 +98,74 @@
int
default 64
+menu "PSP Configuration Options"
+
+config AMDFW_OUTSIDE_CBFS
+ bool
+ default n
+ help
+ The AMDFW (PSP) is typically locatable in cbfs. Select this
+ option to manually attach the generated amdfw.rom outside of
+ cbfs. The location is selected by the FWM position.
+
+config AMD_FWM_POSITION_INDEX
+ int "Firmware Directory Table location (0 to 5)"
+ range 0 5
+ default 0 if BOARD_ROMSIZE_KB_512
+ default 1 if BOARD_ROMSIZE_KB_1024
+ default 2 if BOARD_ROMSIZE_KB_2048
+ default 3 if BOARD_ROMSIZE_KB_4096
+ default 4 if BOARD_ROMSIZE_KB_8192
+ default 5 if BOARD_ROMSIZE_KB_16384
+ help
+ Typically this is calculated by the ROM size, but there may
+ be situations where you want to put the firmware directory
+ table in a different location.
+ 0: 512 KB - 0xFFFA0000
+ 1: 1 MB - 0xFFF20000
+ 2: 2 MB - 0xFFE20000
+ 3: 4 MB - 0xFFC20000
+ 4: 8 MB - 0xFF820000
+ 5: 16 MB - 0xFF020000
+
+comment "AMD Firmware Directory Table set to location for 512KB ROM"
+ depends on AMD_FWM_POSITION_INDEX = 0
+comment "AMD Firmware Directory Table set to location for 1MB ROM"
+ depends on AMD_FWM_POSITION_INDEX = 1
+comment "AMD Firmware Directory Table set to location for 2MB ROM"
+ depends on AMD_FWM_POSITION_INDEX = 2
+comment "AMD Firmware Directory Table set to location for 4MB ROM"
+ depends on AMD_FWM_POSITION_INDEX = 3
+comment "AMD Firmware Directory Table set to location for 8MB ROM"
+ depends on AMD_FWM_POSITION_INDEX = 4
+comment "AMD Firmware Directory Table set to location for 16MB ROM"
+ depends on AMD_FWM_POSITION_INDEX = 5
+
+config AMDFW_CONFIG_FILE
+ string
+ default "src/soc/amd/cezanne/fw.cfg"
+
+config USE_PSPSECUREOS
+ bool
+ default y
+ help
+ Include the PspSecureOs and PspTrustlet binaries in the PSP build.
+
+ If unsure, answer 'y'
+
+config PSP_LOAD_MP2_FW
+ bool
+ default n
+ help
+ Include the MP2 firmwares and configuration into the PSP build.
+
+ If unsure, answer 'n'
+
+config PSP_LOAD_S0I3_FW
+ bool
+ default n
+ help
+
+endmenu
+
endif # SOC_AMD_CEZANNE
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 946e480..d68f080 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -13,4 +13,196 @@
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
+MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
+
+# ROMSIG Normally At ROMBASE + 0x20000
+# Overridden by CONFIG_AMD_FWM_POSITION_INDEX
+# +-----------+---------------+----------------+------------+
+# |0x55AA55AA | | | |
+# +-----------+---------------+----------------+------------+
+# | | PSPDIR ADDR | BIOSDIR ADDR |
+# +-----------+---------------+----------------+
+
+CEZANNE_FWM_POSITION=$(call int-add, \
+ $(call int-subtract, 0xffffffff \
+ $(call int-shift-left, \
+ 0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
+#
+# PSP Directory Table items
+#
+# Certain ordering requirements apply, however these are ensured by amdfwtool.
+# For more information see "AMD Platform Security Processor BIOS Architecture
+# Design Guide for AMD Family 17h Processors" (PID #55758, NDA only).
+#
+
+FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
+
+#ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
+# Enable secure debug unlock
+PSP_SOFTFUSE_BITS += 0
+OPT_TOKEN_UNLOCK="--token-unlock"
+#endif
+
+ifeq ($(CONFIG_USE_PSPSECUREOS),y)
+# types = 0x2
+OPT_PSP_USE_PSPSECUREOS="--use-pspsecureos"
endif
+
+
+#ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y)
+OPT_PSP_LOAD_MP2_FW="--load-mp2-fw"
+#else
+# Disable MP2 firmware loading
+#PSP_SOFTFUSE_BITS += 29
+#endif
+
+#ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y)
+OPT_PSP_LOAD_S0I3_FW="--load-s0i3"
+#endif
+
+#
+# BIOS Directory Table items - proper ordering is managed by amdfwtool
+#
+
+# type = 0x60
+PSP_APCB_FILES=$(APCB_SOURCES)
+
+# type = 0x61
+PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
+
+# type = 0x62
+PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
+PSP_ELF_FILE=$(objcbfs)/bootblock.elf
+PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
+PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
+# type = 0x63 - construct APOB NV base/size from flash map
+# The flashmap section used for this is expected to be named RW_MRC_CACHE
+APOB_NV_SIZE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_SIZE" $(obj)/fmap_config.h | awk '{print $$(NF)}')
+APOB_NV_BASE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_START" $(obj)/fmap_config.h | awk '{print $$(NF)}')
+
+# type = 0x66
+PSP_UCODE_FILE1=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B1.bin
+PSP_UCODE_FILE2=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B0.bin
+PSP_UCODE_FILE3=$(FIRMWARE_LOCATION)/UcodePatch_RV2_A0.bin
+
+ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
+# type = 0x6B - PSP Shared memory location
+ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0)
+PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE)
+_PSP_SHAREDMEM_BASE=$(shell grep _psp_sharedmem_dram $(obj)/cbfs/$(CONFIG_CBFS_PREFIX)/bootblock.map | cut -f1 -d' ')
+PSP_SHAREDMEM_BASE=$(shell printf "0x%s" $(_PSP_SHAREDMEM_BASE))
+endif
+
+# type = 0x52 - PSP Bootloader Userspace Application (verstage)
+PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
+PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN))
+endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK
+
+# type = 0xb - See #55758 (NDA) for bit definitions.
+PSP_SOFTFUSE_BITS += 28
+
+#hardcode post code to eSPI
+PSP_SOFTFUSE_BITS += 15 6
+
+# Helper function to return a value with given bit set
+set-bit=$(call int-shift-left, 1 $(call _toint,$1))
+PSP_SOFTFUSE=$(shell A=$(call int-add, \
+ $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A)
+
+#
+# Build the arguments to amdfwtool (order is unimportant). Missing file names
+# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool.
+#
+
+add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
+
+OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage)
+OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig)
+
+#OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \
+# $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \
+# --instance $(shell printf "%x" $$(($(i)-1))) --apcb ))
+#OPT_PSP_APCB_FILES= --instance 0 --apcb $(APCB_SOURCES) --instance 10 --apcb $(APCB_SOURCES_RECOVERY) --instance 18 --apcb $(APCB_SOURCES_68)
+OPT_PSP_APCB_FILES= --instance 0 --apcb $(APCB_SOURCES) --instance 10 --apcb $(APCB_SOURCES_RECOVERY)
+
+OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
+OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
+OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
+OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
+
+OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem)
+OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size)
+OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size)
+OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base)
+OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
+OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
+OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
+
+OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
+
+#ifeq ($(CONFIG_VBOOT),)
+#OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE)
+#OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE)
+#endif
+
+OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
+
+# Add all the files listed in the config file
+POUND_SIGN=$(call strip_quotes, "\#")
+DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' ))
+
+AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
+ $(OPT_APOB_ADDR) \
+ $(OPT_PSP_BIOSBIN_FILE) \
+ $(OPT_PSP_BIOSBIN_DEST) \
+ $(OPT_PSP_BIOSBIN_SIZE) \
+ $(OPT_PSP_SOFTFUSE) \
+ $(OPT_PSP_USE_PSPSECUREOS) \
+ $(OPT_PSP_LOAD_MP2_FW) \
+ $(OPT_PSP_LOAD_S0I3_FW) \
+ $(OPT_WHITELIST_FILE) \
+ $(OPT_SEC_DEBUG_FILE) \
+ $(OPT_PSP_SHAREDMEM_BASE) \
+ $(OPT_PSP_SHAREDMEM_SIZE) \
+ --combo-capable \
+ $(OPT_TOKEN_UNLOCK) \
+ $(OPT_EFS_SPI_READ_MODE) \
+ $(OPT_EFS_SPI_SPEED) \
+ $(OPT_EFS_SPI_MICRON_FLAG) \
+ --config $(CONFIG_AMDFW_CONFIG_FILE) \
+ --soc-name "Cezanne" \
+ --flashsize $(CONFIG_ROM_SIZE)
+
+$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
+ $(PSP_VERSTAGE_FILE) \
+ $(PSP_VERSTAGE_SIG_FILE) \
+ $$(PSP_APCB_FILES) \
+ $(DEP_FILES) \
+ $(AMDFWTOOL) \
+ $(obj)/fmap_config.h
+ $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
+ rm -f $@
+ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
+ $(AMDFWTOOL) \
+ $(OPT_PSPBTLDR_FILE) \
+ $(AMDFW_COMMON_ARGS) \
+ $(OPT_APOB0_NV_SIZE) \
+ $(OPT_APOB0_NV_BASE) \
+ $(OPT_VERSTAGE_FILE) \
+ $(OPT_VERSTAGE_SIG_FILE) \
+ --location $(shell printf "%#x" $(CEZANNE_FWM_POSITION)) \
+ --multilevel \
+ --output $@
+
+$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
+ rm -f $@
+ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n"
+ $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
+ --maxsize $(PSP_BIOSBIN_SIZE)
+
+cbfs-files-y += apu/amdfw
+apu/amdfw-file := $(obj)/amdfw.rom
+apu/amdfw-position := $(CEZANNE_FWM_POSITION)
+apu/amdfw-type := raw
+
+endif # ($(CONFIG_SOC_AMD_CEZANNE),y)
diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg
new file mode 100644
index 0000000..a482e8c
--- /dev/null
+++ b/src/soc/amd/cezanne/fw.cfg
@@ -0,0 +1,81 @@
+# PSP fw config file
+
+FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP
+
+# type file
+AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn
+PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin
+PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin
+#3
+PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin
+#4?
+PSPNVRAM_FILE PspNvramCZN_2.bin
+
+PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin
+PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn
+#B?
+PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin
+PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin
+PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin
+PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin
+PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin
+#0x22 is not needed?
+#AMD_TOKEN_UNLOCK_FILE TypeId0x22_SecureEmptyToken.bin
+#0x24?
+PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin
+PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin
+#PSP_MP2FW0_WALLE_FILE
+PSP_MP2FW1_FILE TypeId0x125_MP2WALLE_CZN.sbin
+#0x28
+AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin
+#0x29 size=0, useless?
+PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
+#0x2D
+PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
+#0x30
+PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin
+#0x3C
+VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin
+#0x45
+SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin
+#0x44
+UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin
+#0x47
+DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin
+#0x50
+KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin
+#0x51
+KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin
+#0x58
+DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin
+#0x59
+DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin
+#0x54
+RPMC_FILE PspNvramCZN_4.bin
+
+## BDT
+#0x60
+#APCB_CZN_D4_Updatable.bin
+#0x68
+#APCB_CZN_D4_DefaultRecovery.bin
+#0x68
+#APCB_CZN_D4_Updatable_68.bin
+#0x61
+#0x62
+#0x63
+#APOB_NV_FILE APOB_NV_RV.bin
+
+#0x64
+PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin
+#0x65
+PSP_PMUD_FILE1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin
+#0x64
+PSP_PMUI_FILE2 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin
+#0x65
+PSP_PMUD_FILE2 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin
+
+#0x66 #in other place
+#UcodePatch_CZN_A0.bin
+
+#0x6A
+PSP_MP2CFG_FILE MP2FWConfig.sbin
To view, visit change 48528. To unsubscribe, or for help writing mail filters, visit settings.