Attention is currently required from: Hung-Te Lin.
hsin-hsiung wang has uploaded this change for review.
soc/mediatek/mt8192: mt6315: update initial flow
After checking the programming guide, we found there are something wrong
about the sequence of magic key protection flow and clk setting.
Although there is no issue about it, we still want to update it in order
to sync with programming guide.
BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7
---
M src/soc/mediatek/mt8192/mt6315.c
M src/soc/mediatek/mt8192/pmif_spmi.c
2 files changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/51245/1
diff --git a/src/soc/mediatek/mt8192/mt6315.c b/src/soc/mediatek/mt8192/mt6315.c
index 1cb1fe3..7f9b770 100644
--- a/src/soc/mediatek/mt8192/mt6315.c
+++ b/src/soc/mediatek/mt8192/mt6315.c
@@ -91,16 +91,16 @@
{0x16AD, 0x81, 0xFF, 0},
{0x16AE, 0x13, 0x3F, 0},
/* enable magic key protection */
- {0x3A9, 0, 0xFF, 0},
- {0x3A8, 0, 0xFF, 0},
- {0x3A0, 0, 0xFF, 0},
- {0x39F, 0, 0xFF, 0},
- {0x993, 0, 0xFF, 0},
- {0x992, 0, 0xFF, 0},
- {0x1418, 0, 0xFF, 0},
+ {0x3A1, 0, 0xFF, 0},
+ {0x3A2, 0, 0xFF, 0},
{0x1417, 0, 0xFF, 0},
- {0x3a2, 0, 0xFF, 0},
- {0x3a1, 0, 0xFF, 0},
+ {0x1418, 0, 0xFF, 0},
+ {0x992, 0, 0xFF, 0},
+ {0x993, 0, 0xFF, 0},
+ {0x39F, 0, 0xFF, 0},
+ {0x3A0, 0, 0xFF, 0},
+ {0x3A8, 0, 0xFF, 0},
+ {0x3A9, 0, 0xFF, 0},
};
static const struct mt6315_setting init_setting_gpu[] = {
@@ -183,16 +183,16 @@
/* Don't remove this! it's MT6315 for GPU only to disable VBUCK3 */
{0x1440, 0x0, 0x4, 0},
/* enable magic key protection */
- {0x3A9, 0, 0xFF, 0},
- {0x3A8, 0, 0xFF, 0},
- {0x3A0, 0, 0xFF, 0},
- {0x39F, 0, 0xFF, 0},
- {0x993, 0, 0xFF, 0},
- {0x992, 0, 0xFF, 0},
- {0x1418, 0, 0xFF, 0},
+ {0x3A1, 0, 0xFF, 0},
+ {0x3A2, 0, 0xFF, 0},
{0x1417, 0, 0xFF, 0},
- {0x3a2, 0, 0xFF, 0},
- {0x3a1, 0, 0xFF, 0},
+ {0x1418, 0, 0xFF, 0},
+ {0x992, 0, 0xFF, 0},
+ {0x993, 0, 0xFF, 0},
+ {0x39F, 0, 0xFF, 0},
+ {0x3A0, 0, 0xFF, 0},
+ {0x3A8, 0, 0xFF, 0},
+ {0x3A9, 0, 0xFF, 0},
};
static void mt6315_read(u32 slvid, u32 reg, u32 *data)
@@ -219,8 +219,8 @@
mt6315_write(slvid, 0x127, 0x8);
udelay(50);
mt6315_write(slvid, 0x128, 0x8);
- mt6315_write(slvid, 0x3A9, 0);
mt6315_write(slvid, 0x3A8, 0);
+ mt6315_write(slvid, 0x3A9, 0);
}
static void mt6315_init_setting(void)
diff --git a/src/soc/mediatek/mt8192/pmif_spmi.c b/src/soc/mediatek/mt8192/pmif_spmi.c
index 87b003b..9b710d1 100644
--- a/src/soc/mediatek/mt8192/pmif_spmi.c
+++ b/src/soc/mediatek/mt8192/pmif_spmi.c
@@ -62,7 +62,7 @@
/* Software reset */
SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x85);
- SET32_BITFIELDS(&mtk_topckgen->clk_cfg_15,
+ SET32_BITFIELDS(&mtk_topckgen->clk_cfg_15_clr,
CLK_SPMI_MST_SEL, 0x7,
CLK_SPMI_MST_INT, 1,
PDN_SPMI_MST, 1);
To view, visit change 51245. To unsubscribe, or for help writing mail filters, visit settings.