Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32551 )
Change subject: soc/amd/stoneyridge: Correct bugs in lpc.c ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/32551/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32551/1//COMMIT_MSG@12 PS1, Line 12: Since the bridge is enabled in bootblock to allow port 80h, : there is no need to maintain it in ramstage.
I'm ok with that for Stoney, although adding a comment to that effect would probably be good.
I'm in the process of relocating this file to common/blocks, and intend to add an empty weak late_lpc_bridge_enable() with comment. Since the method for enabling has shifted over time, that seems like the best approach to me.
For Picasso, are we just going to assume that the ABL has already enabled it?
We should consider that -- seems like a reasonable assumption it'll already be enabled, but I'll need to verify. It looks like I'd left it like ST, enabled in sb_lpc_port80().