Attention is currently required from: Hung-Te Lin, Arthur Heymans, Shelley Chen, Nico Huber, Furquan Shaikh, Paul Menzel, Angel Pons, Yu-Ping Wu.
8 comments:
File src/soc/mediatek/common/pcie.c:
pcie_ctrl->base + PCIE_CFG_OFFSET_ADDR;
}
I think it's totally fine to move the read32p/write32p to device/mmio. […]
Done, moved to device/mmio.h:
https://review.coreboot.org/c/coreboot/+/62561/1
File src/soc/mediatek/common/pcie.c:
val = read32(ctrl->base + PCIE_SETTING_REG);
val |= PCIE_RC_MODE;
write32(ctrl->base + PCIE_SETTING_REG, val);
`setbits32()` expects a pointer, so this would need to be: […]
I use write32p() instead, is that OK?
Patch Set #10, Line 141: ctrl->base + PCIE_RST_CTRL_REG
After retyping `base` to `uintptr_t`, this needs a cast (or the parameter type of the function point […]
Done
>=
Done
This is incorrect. 'tries' is the number of tries, not elapsed time.
Done
Patch Set #10, Line 193: table + PCIE_ATR_SRC_ADDR_MSB_OFFSET
+1
Done
Is it necessary to report the resource and configure the hardware […]
Done
Patch Set #10, Line 231: return;
Why is this done here and not in `chip_ops->enable_dev()` or […]
Moved to ops->enable(), thanks for your review.
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