Gaggery Tsai has uploaded this change for review.
src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8
This patches adds an initial commit for Intel CML-S RVP board support
and rename the original CML-U RVP to RVPU to avoid confusing. It adds
an additional GBE region in fmd file as well.
TEST=build an image and boot to UEFI payload
Change-Id: Idf723ada53dc441cb9fabc8efb1dcd3da8e0991c
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
---
M src/mainboard/intel/coffeelake_rvp/Kconfig
M src/mainboard/intel/coffeelake_rvp/Kconfig.name
M src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
A src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb
A src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h
6 files changed, 398 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36685/1
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig
index 13e55b3..13cba46 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig
@@ -1,9 +1,9 @@
-if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP
+if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU
- select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU
+ select BOARD_ROMSIZE_KB_16384 if !(BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8)
+ select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8
select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
@@ -11,11 +11,11 @@
select MAINBOARD_HAS_CHROMEOS
select DRIVERS_I2C_HID
select DRIVERS_I2C_GENERIC
- select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8
+ select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 || BOARD_INTEL_COMETLAKE_RVP8
select SOC_INTEL_COMMON_BLOCK_HDA_VERB if !BOARD_INTEL_COFFEELAKE_RVPU
- select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP
+ select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVPU
select MAINBOARD_USES_IFD_EC_REGION
- select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8
+ select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11
config MAINBOARD_DIR
string
@@ -27,12 +27,13 @@
default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11
default "whl_u" if BOARD_INTEL_WHISKEYLAKE_RVP
default "cfl_s" if BOARD_INTEL_COFFEELAKE_RVP8
- default "cml_u" if BOARD_INTEL_COMETLAKE_RVP
+ default "cml_u" if BOARD_INTEL_COMETLAKE_RVPU
+ default "cml_s" if BOARD_INTEL_COMETLAKE_RVP8
config MAINBOARD_PART_NUMBER
string
default "whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP
- default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVP
+ default "cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8
default "cflrvp"
config MAINBOARD_VENDOR
@@ -42,7 +43,7 @@
config MAINBOARD_FAMILY
string
default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP
- default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVP
+ default "Intel_cmlrvp" if BOARD_INTEL_COMETLAKE_RVPU || BOARD_INTEL_COMETLAKE_RVP8
default "Intel_cflrvp"
config CHROMEOS
@@ -53,7 +54,7 @@
config MAX_CPUS
int
- default 12 if BOARD_INTEL_COFFEELAKE_RVP11
+ default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COMETLAKE_RVP8
default 16 if BOARD_INTEL_COFFEELAKE_RVP8
default 8
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name
index 35c0f0f..3e5bf19 100644
--- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name
+++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name
@@ -12,6 +12,10 @@
config BOARD_INTEL_COFFEELAKE_RVP8
bool "-> Coffeelake S U-DIMM DDR4 RVP8"
select SOC_INTEL_COFFEELAKE
-config BOARD_INTEL_COMETLAKE_RVP
+config BOARD_INTEL_COMETLAKE_RVPU
bool "-> Cometlake U DDR4 RVP"
select SOC_INTEL_COMETLAKE
+config BOARD_INTEL_COMETLAKE_RVP8
+ bool "-> Cometlake S U-DIMM DDR4 RVP8"
+ select SOC_INTEL_COMETLAKE
+~
diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
index 62e0f5d..521716a 100644
--- a/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
+++ b/src/mainboard/intel/coffeelake_rvp/chromeos_32MB.fmd
@@ -1,8 +1,9 @@
FLASH@0xfe000000 0x2000000 {
- SI_ALL@0x0 0x1081000 {
+ SI_ALL@0x0 0x1083000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x80000
- SI_ME@0x81000 0x1000000
+ SI_GBE@0x81000 0x2000
+ SI_ME@0x83000 0x1000000
}
SI_BIOS@0x1400000 0xC00000 {
RW_SECTION_A@0x0 0x2d0000 {
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
index ec8f58b..0295d93 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2018 Intel Corporation.
+ * Copyright 2019 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -264,7 +264,7 @@
/* H21 : GPPC_H_21 */
/* H22 : GPPC_H_22 */
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
-#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVP)
+#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVPU)
PAD_CFG_GPO(GPP_H22, 1, PLTRST),
#else
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
@@ -466,8 +466,11 @@
/* F17 : USB2_OC_6 */
/* F18 : USB2_OC_7 */
/* F19 : EDP_VDDEN */
+ PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1),
/* F20 : EDP_BKLTEN */
+ PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1),
/* F21 : EDP_BKLTCTL */
+ PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1),
/* F22 : DDPF_C_TRLCLK */
/* F23 : DDPF_C_TRLDATA */
@@ -512,16 +515,27 @@
PAD_CFG_GPI_SCI_LOW(GPP_H23, NONE, PLTRST, EDGE_SINGLE),
/* I0 : DDPB_HPD_0 */
+ PAD_CFG_NF(GPP_I0, UP_20K, PLTRST, NF1),
/* I1 : DDPC_HPD_1 */
+ PAD_CFG_NF(GPP_I1, UP_20K, PLTRST, NF1),
/* I2 : DPPD_HPD_2 */
+ PAD_CFG_NF(GPP_I2, UP_20K, PLTRST, NF1),
/* I3 : DPPE_HPD_3 */
+ PAD_CFG_NF(GPP_I3, UP_20K, PLTRST, NF1),
/* I4 : EDP_HPD */
+ PAD_CFG_NF(GPP_I4, UP_20K, PLTRST, NF1),
/* I5 : DDPB_C_TRLCLK */
+ PAD_CFG_NF(GPP_I5, UP_20K, PLTRST, NF1),
/* I6 : DDPB_C_TRLDATA */
+ PAD_CFG_NF(GPP_I6, UP_20K, PLTRST, NF1),
/* I7 : DDPC_C_TRLCLK */
+ PAD_CFG_NF(GPP_I7, UP_20K, PLTRST, NF1),
/* I8 : DDPC_C_TRLDATA */
+ PAD_CFG_NF(GPP_I8, UP_20K, PLTRST, NF1),
/* I9 : DDPD_C_TRLCLK */
+ PAD_CFG_NF(GPP_I9, UP_20K, PLTRST, NF1),
/* I10 : DDPD_C_TRLDATA */
+ PAD_CFG_NF(GPP_I10, UP_20K, PLTRST, NF1),
/* I11 : M2_SKT2_C_FG0 */
/* I12 : M2_SKT2_CFG1 */
/* I13 : M2_SKT2_C_FG2 */
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb
new file mode 100644
index 0000000..7a93af0
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/devicetree.cb
@@ -0,0 +1,163 @@
+chip soc/intel/cannonlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ # FSP configuration
+ register "SaGv" = "SaGv_Enabled"
+ register "RMT" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC7)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC7)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC6)"
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC4)"
+ register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)"
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[10]" = "USB2_PORT_MID(OC5)"
+ register "usb2_ports[11]" = "USB2_PORT_MID(OC5)"
+ register "usb2_ports[12]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[13]" = "USB2_PORT_EMPTY"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC7)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC3)"
+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)"
+ register "usb3_ports[8]" = "USB3_PORT_EMPTY"
+ register "usb3_ports[9]" = "USB3_PORT_EMPTY"
+
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsEnable[3]" = "1"
+ register "SataPortsEnable[4]" = "1"
+ register "SataPortsEnable[5]" = "1"
+ register "SataPortsEnable[6]" = "1"
+ register "SataPortsEnable[7]" = "1"
+
+ register "PchHdaDspEnable" = "0"
+ register "PchHdaAudioLinkHda" = "1"
+
+ register "PcieRpEnable[0]" = "0"
+ register "PcieRpEnable[1]" = "0"
+
+ # PCIe root port 3 for GBe LAN
+ register "PcieRpEnable[2]" = "1"
+ # RP 3 uses CLK SRC 8
+ register "PcieClkSrcUsage[8]" = "2"
+ # ClkReq-to-ClkSrc mapping for CLK SRC 8
+ register "PcieClkSrcClkReq[8]" = "8"
+
+ # PCIe root port 4 for M.2 Wi-Fi
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+ # RP 4 uses CLK SRC 0
+ register "PcieClkSrcUsage[0]" = "3"
+ # ClkReq-to-ClkSrc mapping for CLK SRC 0
+ register "PcieClkSrcClkReq[0]" = "0"
+
+ # PCIe root port 9 for X4 slot
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpEnable[10]" = "1"
+ register "PcieRpEnable[11]" = "1"
+ # RP 9 uses CLK SRC 4
+ register "PcieClkSrcUsage[4]" = "8"
+
+ # PCIe root port 13 for GBe LAN
+ register "PcieRpEnable[12]" = "1"
+ # RP 13 uses CLK SRC 1
+ register "PcieClkSrcUsage[1]" = "12"
+ # ClkReq-to-ClkSrc mapping for CLK SRC 1
+ register "PcieClkSrcClkReq[1]" = "1"
+
+ # PCIe root port 17 for X4 M.2 SSD
+ register "PcieRpEnable[16]" = "1"
+ register "PcieRpEnable[17]" = "1"
+ register "PcieRpEnable[18]" = "1"
+ register "PcieRpEnable[19]" = "1"
+ # RP 17 uses CLK SRC 2
+ register "PcieClkSrcUsage[2]" = "16"
+ # ClkReq-to-ClkSrc mapping for CLK SRC 1
+ register "PcieClkSrcClkReq[2]" = "2"
+
+ # PCIe root port 21 for X4 slot
+ register "PcieRpEnable[20]" = "1"
+ register "PcieRpEnable[21]" = "1"
+ register "PcieRpEnable[22]" = "1"
+ register "PcieRpEnable[23]" = "1"
+ # RP 21 uses CLK SRC 5
+ register "PcieClkSrcUsage[5]" = "20"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # HECI
+ register "HeciEnabled" = "1"
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on end # SA Thermal device
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ chip drivers/intel/wifi
+ register "wake" = "PME_B0_EN_BIT"
+ device pci 14.3 on end # CNVi wifi
+ end
+ device pci 14.5 on end # SDCard
+ device pci 15.0 on end # I2C 0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # I2C #4
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on end # PCI Express Port 9 X4 SLOT 1
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express Port 13
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1b.0 on end # PCI Express Port 17 M.2 SSD
+ device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on end # LPC
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h
new file mode 100644
index 0000000..f921f3f
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/include/variant/hda_verb.h
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Damien Zammit <damien@zamaudio.com>
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef HDA_VERB_H
+#define HDA_VERB_H
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+
+ /*
+ * VerbTable: CFL Display Audio Codec
+ * Revision ID = 0xFF
+ * Codec Vendor: 0x8086280B
+ */
+
+ 0x8086280B,
+ 0xFFFFFFFF,
+ 0x00000005,
+
+ /*
+ * Display Audio Verb Table
+ * For GEN9, the Vendor Node ID is 08h
+ * Port to be exposed to the inbox driver in the vanilla mode
+ * PORT C - BIT[7:6] = 01b
+ */
+ 0x00878140,
+ 0x00878140,
+ 0x00878140,
+ 0x00878140,
+ /* Pin Widget 5 - PORT B - Configuration Default: 0x18560010 */
+ 0x00571C10,
+ 0x00571D00,
+ 0x00571E56,
+ 0x00571F18,
+ /* Pin Widget 6 - PORT C - Configuration Default: 0x18560020 */
+ 0x00671C20,
+ 0x00671D00,
+ 0x00671E56,
+ 0x00671F18,
+ /* Pin Widget 7 - PORT D - Configuration Default: 0x18560030 */
+ 0x00771C30,
+ 0x00771D00,
+ 0x00771E56,
+ 0x00771F18,
+ /* Disable the third converter and third Pin (NID 08h) */
+ 0x00878140,
+ 0x00878140,
+ 0x00878140,
+ 0x00878140,
+
+ /* ALC700 */
+ 0x10EC0700,
+ 0xFFFFFFFF,
+ 0x00000015,
+
+ /*
+ * HDA Codec Subsystem ID Verb-table
+ * HDA Codec Subsystem ID : 0x10EC112C
+ */
+ 0x0017202C,
+ 0x00172111,
+ 0x001722EC,
+ 0x00172310,
+
+ /*
+ * Pin Widget Verb-table
+ * Widget node 0x01
+ */
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ /* Pin widget 0x12 - DMIC */
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ /* Pin widget 0x13 - DMIC */
+ 0x01371CF0,
+ 0x01371D11,
+ 0x01371E11,
+ 0x01371F41,
+ /* Pin widget 0x14 - FRONT (Port-D) */
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ /* Pin widget 0x15 - I2S-OUT */
+ 0x01571C10,
+ 0x01571D01,
+ 0x01571E17,
+ 0x01571F90,
+ /* Pin widget 0x16 - LINE3 (Port-B) */
+ 0x01671C20,
+ 0x01671D10,
+ 0x01671E01,
+ 0x01671F01,
+ /* Pin widget 0x17 - I2S-OUT */
+ 0x01771CF0,
+ 0x01771D11,
+ 0x01771E11,
+ 0x01771F41,
+ /* Pin widget 0x18 - I2S-IN */
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ /* Pin widget 0x19 - MIC2 (Port-F) */
+ 0x01971C30,
+ 0x01971D90,
+ 0x01971EA1,
+ 0x01971F02,
+ /* Pin widget 0x1A - LINE1 (Port-C) */
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ /* Pin widget 0x1B - LINE2 (Port-E) */
+ 0x01B71C40,
+ 0x01B71D90,
+ 0x01B71EA1,
+ 0x01B71F01,
+ /* Pin widget 0x1D - PC-BEEP */
+ 0x01D71C69,
+ 0x01D71D84,
+ 0x01D71E45,
+ 0x01D71F40,
+ /* Pin widget 0x1E - S/PDIF-OUT */
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ /* Pin widget 0x1F - S/PDIF-IN */
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ /* Pin widget 0x21 - P-OUT (Port-I) */
+ 0x02171C2F,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F02,
+ /* Pin widget 0x29 - I2S-IN */
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ /*
+ * Widget node 0x20 : MIC2-Vrefo-R and MIC2-vrefo-L
+ * to independent control
+ */
+ 0x02050045,
+ 0x02045089,
+ 0x0205004A,
+ 0x0204201B,
+ /* Widget node 0x20 - 1 */
+ 0x05850000,
+ 0x05843888,
+ 0x0205006F,
+ 0x02042C0B,
+ /*
+ * Widget node 0x20 - 2 : Line2-JD gating MIC2-Vrefo-R,
+ * P-JD gating MIC2-vrefo-L
+ */
+ 0x0205006B,
+ 0x02044260,
+ 0x05B50010,
+ 0x05B45C1D,
+
+ /* Widget node 0X20 for ALC1305 */
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+};
+
+const u32 pc_beep_verbs[] = {
+};
+
+AZALIA_ARRAY_SIZES;
+#endif
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