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1 comment:
Commit Message:
Patch Set #1, Line 9: Some variants only support 4 PCIe ports so there is no need to have
Maybe rephrase as "variants of southbridge". […]
The function disable bits for the PCIe ports on those variants is RO and always set.
I'll update the commit message.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484
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