1 comment:
File src/arch/x86/postcar_loader.c:
Patch Set #2, Line 135: MTRR_TYPE_WRPROT
This type is inherently wrong as you'll be writing to this memory for loading purposes. […]
yes, i will come up with more debug data, right now my observation says, if i make it WB and the moment write appears into this area, it just hangs..
Here is the log from hatch-cml with romstage->postcar->ramstage (existing model)
top_of_ram = 0x9a000000
>>>>>>>>
here we are setting new MTRR
0x0000000099000006: PHYBASE2: Address = 0x0000000099000000, WB
0x0000007fff000800: PHYMASK2: Length = 0x0000000001000000, Valid
>>>>>>>>
MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
MTRR Range: Start=ff000000 End=0 (Size 1000000)
CBFS: 'VBOOT' located CBFS at [1410000:151f280)
CBFS: Locating 'fallback/postcar'
CBFS: Found @ offset f1000 size 4688
Decompressing stage fallback/postcar @ 0x99c1ffc0 (34744 bytes)
Loading module at 99c20000 with entry 99c20000. filesize: 0x43d8 memsize: 0x8778
Processing 149 relocs. Offset value of 0x97c20000
>>>>>>>>
hang here, unable to execute postcar
>>>>>>>>
but with WP, i don't see such issue, this tells me when ever write operation happens into this new MTRR range, its gone.
in cache_as_ram.S we have actually created direct caching for Data region (RW), marked as WB
#1
With this we were making below region for data (marked as WB, RW enable for caching)
1.
0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB
0x0000007ffffc0800: PHYMASK0: Length = 0x0000000000040000, Valid
And 1 code (RO) region marked as WP
#2
0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP
0x0000007fff000800: PHYMASK1: Length = 0x0000000001000000, Valid
Need to understand if there any limitation of marking more than 1 region as WB as we are in NEM enhanced mode and already cached #1 above region before enabling NEM enhanced mode ?
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