Gaggery Tsai has uploaded this change for review.
mb/google/fizz: Override IccMax settings
According to Intel document #559100 KBL EDS v2.8, section 7.2
DC specifications, the IccMax setting for KBL-U, KBL-U42 and
Celeron are different. This patch sets Celeron as default SKU
in device tree and overrides the IccMax settings for KBL-U and
KBL-U42 at pre-FSPS.
+----------------+-------------+---------------+-------+-------+
| Domain/Setting | SA | IA | GTUS | GTS |
+----------------+-------------+---------------+-------+-------+
| IccMax | 6A(U42) | 64A(U42) | 31A | 31A |
| | 4.5A(Others)| 29A(Celeron) | 31A | 31A |(Default)
| | | 32A(i3/i5) | 31A | 31A |
+----------------+-------------+-------+-------+-------+-------+
BUG=b:71369428
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42,
KBL-U and Celeron SKUs are identified correctly and IccMax settings
are passed to FSPS correctly.
Change-Id: I32ffe0cb73981850005b20fefb6664cfab74fbca
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
---
A src/mainboard/google/fizz/common.h
M src/mainboard/google/fizz/devicetree.cb
M src/mainboard/google/fizz/mainboard.c
M src/mainboard/google/fizz/ramstage.c
4 files changed, 85 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/23020/1
diff --git a/src/mainboard/google/fizz/common.h b/src/mainboard/google/fizz/common.h
new file mode 100644
index 0000000..f5714ba
--- /dev/null
+++ b/src/mainboard/google/fizz/common.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_COMMON_H__
+#define __MAINBOARD_COMMON_H__
+
+#define FIZZ_SKU_ID_I7_U42 0x4
+#define FIZZ_SKU_ID_I3 0x1
+#define FIZZ_SKU_ID_I5 0x2
+#define FIZZ_PL2_I7_U42 44
+#define FIZZ_PL2_OTHERS 29
+
+#define FIZZ_ICCMAX_SA_I7_U42 6
+#define FIZZ_ICCMAX_CORE_I7_U42 64
+#define FIZZ_ICCMAX_CORE_I3_I5 32
+
+uint8_t board_sku_id(void);
+
+#endif
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index e94dd26..5550328 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -102,20 +102,23 @@
register "pirqg_routing" = "PCH_IRQ11"
register "pirqh_routing" = "PCH_IRQ11"
- # VR Settings Configuration for 4 Domains
- #+----------------+-------+-------+-------+-------+
- #| Domain/Setting | SA | IA | GTUS | GTS |
- #+----------------+-------+-------+-------+-------+
- #| Psi1Threshold | 20A | 20A | 20A | 20A |
- #| Psi2Threshold | 4A | 5A | 5A | 5A |
- #| Psi3Threshold | 1A | 1A | 1A | 1A |
- #| Psi3Enable | 1 | 1 | 1 | 1 |
- #| Psi4Enable | 1 | 1 | 1 | 1 |
- #| ImonSlope | 0 | 0 | 0 | 0 |
- #| ImonOffset | 0 | 0 | 0 | 0 |
- #| IccMax | 7A | 34A | 35A | 35A |
- #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
- #+----------------+-------+-------+-------+-------+
+ # Initial VR Settings Configuration for 4 Domains
+ # Some SKUs needs to be overriden somewhere else.
+ #+----------------+-------------+---------------+-------+-------+
+ #| Domain/Setting | SA | IA | GTUS | GTS |
+ #+----------------+-------------+---------------+-------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 |
+ #| IccMax | 6A(U42) | 64A(U42) | 31A | 31A |
+ #| | 4.5A(Others)| 29A(Celeron) | 31A | 31A |(Default)
+ #| | | 32A(i3/i5) | 31A | 31A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------------+-------+-------+-------+-------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20),
@@ -125,7 +128,7 @@
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(7),
+ .icc_max = VR_CFG_AMP(4.5),
.voltage_limit = 1520,
}"
@@ -138,7 +141,7 @@
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(34),
+ .icc_max = VR_CFG_AMP(29),
.voltage_limit = 1520,
}"
@@ -151,7 +154,7 @@
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(35),
+ .icc_max = VR_CFG_AMP(31),
.voltage_limit = 1520,
}"
@@ -164,7 +167,7 @@
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
- .icc_max = VR_CFG_AMP(35),
+ .icc_max = VR_CFG_AMP(31),
.voltage_limit = 1520,
}"
diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index 98c0078..4aa72bd 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -21,6 +21,7 @@
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <mainboard/google/fizz/gpio.h>
+#include <mainboard/google/fizz/common.h>
#include <smbios.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
@@ -28,9 +29,6 @@
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#define FIZZ_SKU_ID_I7_U42 0x4
-#define FIZZ_PL2_I7_U42 44
-#define FIZZ_PL2_OTHERS 29
/*
* For type-C chargers, set PL2 to 90% of max power to account for
* cable loss and FET Rdson loss in the path from the source.
@@ -81,7 +79,7 @@
static const char *oem_id = "GOOGLE";
static const char *oem_table_id = "FIZZ";
-static uint8_t board_sku_id(void)
+uint8_t board_sku_id(void)
{
static int id = -1;
const gpio_t sku_id_gpios[] = {
diff --git a/src/mainboard/google/fizz/ramstage.c b/src/mainboard/google/fizz/ramstage.c
index 6dafe65..a297828 100644
--- a/src/mainboard/google/fizz/ramstage.c
+++ b/src/mainboard/google/fizz/ramstage.c
@@ -14,10 +14,40 @@
*/
#include <soc/ramstage.h>
-
+#include <soc/pci_devs.h>
#include "gpio.h"
+#include "common.h"
+
+static void mainboard_setup_iccmax(config_t *conf)
+{
+ int sku_id = board_sku_id();
+ /*
+ * Iccmax table from Doc #55910 Section 7.2 DC Specifications
+ * +----------------+-------------+---------------+-------+-------+
+ * | Domain/Setting | SA | IA | GTUS | GTS |
+ * +----------------+-------------+---------------+-------+-------+
+ * | IccMax | 6A(U42) | 64A(U42) | 31A | 31A |
+ * | | 4.5A(Others)| 29A(Celeron) | 31A | 31A |(Default)
+ * | | | 32A(i3/i5) | 31A | 31A |
+ * +----------------+-------------+-------+-------+-------+-------+
+ */
+
+ /* Assumed default Iccmax setting in device tree is for Celeron */
+ if (sku_id == FIZZ_SKU_ID_I7_U42) {
+ conf->domain_vr_config[VR_SYSTEM_AGENT].icc_max = VR_CFG_AMP(FIZZ_ICCMAX_SA_I7_U42);
+ conf->domain_vr_config[VR_IA_CORE].icc_max = VR_CFG_AMP(FIZZ_ICCMAX_CORE_I7_U42);
+ }
+
+ if (sku_id == FIZZ_SKU_ID_I3 || sku_id == FIZZ_SKU_ID_I5)
+ conf->domain_vr_config[VR_IA_CORE].icc_max = VR_CFG_AMP(FIZZ_ICCMAX_CORE_I3_I5);
+
+}
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
+ device_t root = SA_DEV_ROOT;
+ config_t *conf = root->chip_info;
+
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+ mainboard_setup_iccmax(conf);
}
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