Kyösti Mälkki has uploaded this change for review.
device,drivers/: Drop some __SIMPLE_DEVICE__ use
The simple PCI config accessors are always available
under names pci_s_[read|write]_configX.
Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
M src/commonlib/storage/pci_sdhci.c
M src/device/pci_early.c
M src/device/pci_ops.c
M src/drivers/uart/oxpcie_early.c
4 files changed, 25 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35669/1
diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c
index de248b7..abc093f 100644
--- a/src/commonlib/storage/pci_sdhci.c
+++ b/src/commonlib/storage/pci_sdhci.c
@@ -12,10 +12,6 @@
* GNU General Public License for more details.
*/
-#if ENV_RAMSTAGE
-#define __SIMPLE_DEVICE__ 1
-#endif
-
#include <arch/early_variables.h>
#include <commonlib/sdhci.h>
#include <device/pci.h>
@@ -54,11 +50,11 @@
return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr);
}
-struct sd_mmc_ctrlr *new_pci_sdhci_controller(uint32_t dev)
+struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev)
{
uint32_t addr;
- addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ addr = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0);
if (addr == ((uint32_t)~0)) {
sdhc_error("Error: PCI SDHCI not found\n");
return NULL;
diff --git a/src/device/pci_early.c b/src/device/pci_early.c
index 880480d..d50d1e6 100644
--- a/src/device/pci_early.c
+++ b/src/device/pci_early.c
@@ -11,8 +11,6 @@
* GNU General Public License for more details.
*/
-#define __SIMPLE_DEVICE__
-
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
@@ -24,26 +22,26 @@
u16 reg16;
/* First we reset the secondary bus. */
- reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
+ reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
reg16 |= (1 << 6); /* SRESET */
- pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
+ pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
/* Assume we don't have to wait here forever */
/* Read back and clear reset bit. */
- reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
+ reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
reg16 &= ~(1 << 6); /* SRESET */
- pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
+ pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
}
static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary)
{
/* Disable config transaction forwarding. */
- pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
- pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
+ pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
+ pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
/* Enable config transaction forwarding. */
- pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
- pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
+ pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
+ pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
}
static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size)
@@ -51,21 +49,21 @@
u16 reg16;
/* Disable MMIO window behind the bridge. */
- reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
+ reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
- pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
- pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);
+ pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
+ pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);
if (!size)
return;
/* Enable MMIO window behind the bridge. */
- pci_write_config32(p2p_bridge, PCI_MEMORY_BASE,
+ pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE,
((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0));
- reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
+ reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
- pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
+ pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16);
}
void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size)
@@ -84,7 +82,8 @@
pci_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size);
for (timeout = 20000; timeout; timeout--) {
- u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID);
+ pci_devfn_t dbg_dev = PCI_DEV(secondary, dev, 0);
+ u32 id = pci_s_read_config32(dbg_dev, PCI_VENDOR_ID);
if (id != 0 && id != 0xffffffff && id != 0xffff0001)
break;
udelay(10);
@@ -123,7 +122,7 @@
{
for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
unsigned int id;
- id = pci_read_config32(dev, 0);
+ id = pci_s_read_config32(dev, 0);
if (id == pci_id)
return dev;
}
@@ -139,7 +138,7 @@
for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
unsigned int id;
- id = pci_read_config32(dev, 0);
+ id = pci_s_read_config32(dev, 0);
if (id == pci_id)
return dev;
}
diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c
index 6f42978..431160e 100644
--- a/src/device/pci_ops.c
+++ b/src/device/pci_ops.c
@@ -11,8 +11,6 @@
* GNU General Public License for more details.
*/
-#define __SIMPLE_DEVICE__
-
#include <stdint.h>
#include <console/console.h>
#include <device/pci.h>
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
index b990401..eb6f880 100644
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
-#define __SIMPLE_DEVICE__
-
#include <stdint.h>
#include <stddef.h>
#include <device/pci_ops.h>
@@ -31,7 +29,7 @@
{
pci_devfn_t device = PCI_DEV(bus, dev, 0);
- u32 id = pci_read_config32(device, PCI_VENDOR_ID);
+ u32 id = pci_s_read_config32(device, PCI_VENDOR_ID);
switch (id) {
case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
/* On this device function 0 is the parallel port, and
@@ -39,7 +37,7 @@
* the UART.
*/
device = PCI_DEV(bus, dev, 3);
- id = pci_read_config32(device, PCI_VENDOR_ID);
+ id = pci_s_read_config32(device, PCI_VENDOR_ID);
if (id != 0xc11b1415)
return -1;
break;
@@ -56,12 +54,12 @@
return -1;
/* Setup base address on device */
- pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
+ pci_s_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
/* Enable memory on device */
- u16 reg16 = pci_read_config16(device, PCI_COMMAND);
+ u16 reg16 = pci_s_read_config16(device, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
- pci_write_config16(device, PCI_COMMAND, reg16);
+ pci_s_write_config16(device, PCI_COMMAND, reg16);
car_set_var(oxpcie_present, 1);
return 0;
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