Hello Naresh Solanki, Aaron Durbin, Patrick Rudolph, Subrata Banik, Aamir Bohra, Patrick Rudolph, Duncan Laurie, Rizwan Qureshi, Shelley Chen, build bot (Jenkins), Furquan Shaikh, V Sowmya, Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31284
to look at the new patch set (#19).
Change subject: soc/intel/cannonlake: Add required FSP UPD changes for CML ......................................................................
soc/intel/cannonlake: Add required FSP UPD changes for CML
This patch adds required FSP UPD changes for CometLake SoC. Also this patch tries to create common parse logic for CometLake as well as cannonlake SOC.
We parse device tree parameters for PCI devices and fill values in FSP UPDs. We fill UPDs based on pci device config as well as SerialIoDev config of devicetree. For PCI devices, if PCI device is disabled from devicetree, we'll assign disable value to FSP UPD. In case devicetree doesn't fill this parameter or value is invalid in SerialIoDev config, default mode will be set to PCI. In case of valid value, we'll fill the same value into FSP UPD.
BUG=none BRANCH=none TEST=check if CML board boots and proper UPD values are filled.
Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d Signed-off-by: Subrata Banik subrata.banik@intel.com Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/serialio.h 3 files changed, 108 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31284/19