HAOUAS Elyes has uploaded this change for review.
sb/i82371eb/acpi: Convert to ASL 2.0 syntax
Change-Id: I45b803ec22fca6a6a620d53ad52502e0d48ae7cd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/southbridge/intel/i82371eb/acpi/intx.asl
M src/southbridge/intel/i82371eb/acpi/pirq.asl
2 files changed, 73 insertions(+), 73 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45736/1
diff --git a/src/southbridge/intel/i82371eb/acpi/intx.asl b/src/southbridge/intel/i82371eb/acpi/intx.asl
index c55ff33..6a6de13 100644
--- a/src/southbridge/intel/i82371eb/acpi/intx.asl
+++ b/src/southbridge/intel/i82371eb/acpi/intx.asl
@@ -8,40 +8,40 @@
})
/* adapted from ma78gm/dsdt.asl */
-#define PCI_INTX_DEV(intx, pinx, uid) \
-Device(intx) { \
- Name(_HID, EISAID("PNP0C0F")) \
- Name(_UID, uid) \
- \
- Method(_STA, 0) { \
- If (And(pinx, 0x80)) { \
- Return(0x09) \
- } \
- Return(0x0B) \
- } \
- \
- Method(_DIS ,0) { \
- Store(0x80, pinx) \
- } \
- \
- Method(_PRS ,0) { \
- Return(IRQP) \
- } \
- \
- Method(_CRS ,0) { \
- CreateWordField(IRQB, 1, IRQN) \
- ShiftLeft(1, And(pinx, 0x0f), IRQN) \
- Return(IRQB) \
- } \
- \
- Method(_SRS, 1) { \
- CreateWordField(ARG0, 1, IRQM) \
- \
- /* Use lowest available IRQ */ \
- FindSetRightBit(IRQM, Local0) \
- if (Local0) { \
- Decrement(Local0) \
- } \
- Store(Local0, pinx) \
- } \
+#define PCI_INTX_DEV(intx, pinx, uid) \
+Device(intx) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ \
+ Method(_STA, 0) { \
+ If (pinx & 0x80) { \
+ Return (0x09) \
+ } \
+ Return (0x0B) \
+ } \
+ \
+ Method(_DIS ,0) { \
+ pinx = 0x80 \
+ } \
+ \
+ Method(_PRS ,0) { \
+ Return(IRQP) \
+ } \
+ \
+ Method(_CRS ,0) { \
+ CreateWordField(IRQB, 1, IRQN) \
+ IRQN = 1 << (pinx & 0x0f) \
+ Return (IRQB) \
+ } \
+ \
+ Method(_SRS, 1) { \
+ CreateWordField(ARG0, 1, IRQM) \
+ \
+ /* Use lowest available IRQ */ \
+ FindSetRightBit(IRQM, Local0) \
+ if (Local0) { \
+ Local0-- \
+ } \
+ pinx = Local0 \
+ } \
}
diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl
index 176906a..5ef4d32 100644
--- a/src/southbridge/intel/i82371eb/acpi/pirq.asl
+++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl
@@ -18,43 +18,43 @@
})
/* adapted from ma78gm/dsdt.asl */
-#define PCI_INTX_DEV(intx, pinx, uid) \
-Device(intx) { \
- Name(_HID, EISAID("PNP0C0F")) \
- Name(_UID, uid) \
- \
- Method(_STA, 0) { \
- If (And(pinx, 0x80)) { \
- Return(0x09) \
- } \
- Return(0x0B) \
- } \
- \
- Method(_DIS ,0) { \
- Store(0x80, pinx) \
- } \
- \
- Method(_PRS ,0) { \
- Return(IRQP) \
- } \
- \
- Method(_CRS ,0) { \
- CreateWordField(IRQB, 1, IRQN) \
- ShiftLeft(1, And(pinx, 0x0f), IRQN) \
- Return(IRQB) \
- } \
- \
- Method(_SRS, 1) { \
- CreateWordField(ARG0, 1, IRQM) \
- \
- /* Use lowest available IRQ */ \
- FindSetRightBit(IRQM, Local0) \
- if (Local0) { \
- Decrement(Local0) \
- } \
- Store(Local0, pinx) \
- } \
-} \
+#define PCI_INTX_DEV(intx, pinx, uid) \
+Device(intx) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ \
+ Method(_STA, 0) { \
+ If (pinx & 0x80) { \
+ Return (0x09) \
+ } \
+ Return (0x0B) \
+ } \
+ \
+ Method(_DIS ,0) { \
+ pinx = 0x80 \
+ } \
+ \
+ Method(_PRS ,0) { \
+ Return (IRQP) \
+ } \
+ \
+ Method(_CRS ,0) { \
+ CreateWordField(IRQB, 1, IRQN) \
+ IRQN = 1 << (pinx & 0x0f) \
+ Return (IRQB) \
+ } \
+ \
+ Method(_SRS, 1) { \
+ CreateWordField(ARG0, 1, IRQM) \
+ \
+ /* Use lowest available IRQ */ \
+ FindSetRightBit(IRQM, Local0) \
+ if (Local0) { \
+ Local0-- \
+ } \
+ pinx = Local0 \
+ } \
+} \
PCI_INTX_DEV(LNKA, PRTA, 1)
PCI_INTX_DEV(LNKB, PRTB, 2)
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