Angel Pons has uploaded this change for review.

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cpu/intel/socket_m/Makefile.inc: Order entries

Group lines by stages, then subdirs, then microcode. Within groups,
order in ascending count of `../` in prefix and then alphabetically.
Group CPU models separately from other subdirs, as they are special.

Tested with BUILD_TIMELESS=1, Getac P470 remains identical.

Change-Id: Ie3e4574512e6f3e3f12209ba72e90e87c180b0cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/cpu/intel/socket_m/Makefile.inc
1 file changed, 16 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44221/1

diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc
index 61e4e58..d79e082 100644
--- a/src/cpu/intel/socket_m/Makefile.inc
+++ b/src/cpu/intel/socket_m/Makefile.inc
@@ -1,16 +1,19 @@
-subdirs-y += ../model_6ex
-subdirs-y += ../model_6fx
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-subdirs-y += ../microcode
-subdirs-y += ../hyperthreading
-subdirs-y += ../speedstep
-
-bootblock-y += ../car/core2/cache_as_ram.S
 bootblock-y += ../car/bootblock.c
-postcar-y += ../car/p4-netburst/exit_car.S
+bootblock-y += ../car/core2/cache_as_ram.S
 
 romstage-y += ../car/romstage.c
+
+postcar-y += ../car/p4-netburst/exit_car.S
+
+subdirs-y += ../model_6ex
+subdirs-y += ../model_6fx
+
+subdirs-y += ../hyperthreading
+subdirs-y += ../microcode
+subdirs-y += ../speedstep
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/smm
+subdirs-y += ../../x86/tsc
+

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