Angel Pons has uploaded this change for review.
nb/intel/x4x: Refactor `decode_pciebar`
Constify and eliminate local variables where possible to ease reading.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: I6d2937146a4764823cfc45c69a09f734b2525860
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/northbridge/intel/x4x/memmap.c
1 file changed, 5 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/44142/1
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 6d40faf..8a69ba8 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -61,11 +61,7 @@
{
*base = 0;
*len = 0;
- const pci_devfn_t dev = PCI_DEV(0, 0, 0);
- u32 pciexbar = 0;
- u32 pciexbar_reg;
- u32 reg32;
- int max_buses;
+
const struct {
u16 num_buses;
u32 addr_mask;
@@ -76,16 +72,16 @@
{0, 0},
};
- pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
+ const u32 pciexbar_reg = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO);
if (!(pciexbar_reg & 1)) {
printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
return 0;
}
- reg32 = (pciexbar_reg >> 1) & 3;
- pciexbar = pciexbar_reg & busmask[reg32].addr_mask;
- max_buses = busmask[reg32].num_buses;
+ const u32 index = (pciexbar_reg >> 1) & 3;
+ const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
+ const int max_buses = busmask[index].num_buses;
if (!pciexbar) {
printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
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