Subrata Banik has uploaded this change for review.
soc/intel/{cnl, dnv, icl, skl}: Make top_of_ram align
This patch makes top_of_ram aligned in order to meet MTRR
alignment requirments.
Change-Id: I62d89cb35d8b5082d49c80aea55ac34dbb3b10ff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
4 files changed, 27 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35029/1
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 9e2f2f8..d83da7f 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -133,6 +133,7 @@
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
+ const size_t top_of_ram_size = 16*MiB;
struct chipset_power_state *ps = pmc_get_power_state();
console_init();
@@ -155,12 +156,14 @@
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
+ * a safe bet to cover ramstage. This satisfies MTRR alignment
+ * requirements as well.
*/
- top_of_ram = (uintptr_t) cbmem_top();
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+ top_of_ram -= top_of_ram_size;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size,
+ MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index af65d38..0d8d4c8 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -142,6 +142,7 @@
struct postcar_frame pcf;
uintptr_t top_of_ram;
+ const size_t top_of_ram_size = 16*MiB;
console_init();
@@ -164,10 +165,12 @@
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
* 16 megs under cbmem top which is a safe bet to cover ramstage.
+ * This satisfies MTRR alignment requirements as well.
*/
- top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB,
- MTRR_TYPE_WRBACK);
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
+ top_of_ram -= top_of_ram_size;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size,
+ MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 4d0cc17..a083788 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -117,6 +117,7 @@
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
+ const size_t top_of_ram_size = 16*MiB;
struct chipset_power_state *ps = pmc_get_power_state();
console_init();
@@ -139,12 +140,14 @@
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
+ * a safe bet to cover ramstage. This satisfies MTRR alignment
+ * requirements as well.
*/
- top_of_ram = (uintptr_t) cbmem_top();
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+ top_of_ram -= top_of_ram_size;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size,
+ MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 1d925b3..0977614 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -145,6 +145,7 @@
bool s3wake;
struct postcar_frame pcf;
uintptr_t top_of_ram;
+ const size_t top_of_ram_size = 16*MiB;
struct chipset_power_state *ps;
console_init();
@@ -166,12 +167,14 @@
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs under cbmem top which is
- * a safe bet to cover ramstage.
+ * a safe bet to cover ramstage. This satisfies MTRR alignment
+ * requirements as well.
*/
- top_of_ram = (uintptr_t) cbmem_top();
+ top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), top_of_ram_size);
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
- top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+ top_of_ram -= top_of_ram_size;
+ postcar_frame_add_mtrr(&pcf, top_of_ram, top_of_ram_size,
+ MTRR_TYPE_WRBACK);
if (CONFIG(HAVE_SMI_HANDLER)) {
/* Cache the TSEG region. */
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