Mike Hsieh has uploaded this change for review.
mb/google/sarien/variants/arcada: Update thermal configuration for DPTF
Update dptf for arcada DVT2.
BUG=b:123924662
TEST=Built and tested on arcada system
Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Change-Id: I302b7cd4c7e0579acb5482800241b5229cfc49f7
---
M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
1 file changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/33360/1
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
index 4d38071..73e1dec 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
@@ -13,26 +13,26 @@
* GNU General Public License for more details.
*/
-#define DPTF_CPU_PASSIVE 90
-#define DPTF_CPU_CRITICAL 105
+#define DPTF_CPU_PASSIVE 98
+#define DPTF_CPU_CRITICAL 108
/* Skin Sensor for CPU VR temperature monitor */
#define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "Skin"
-#define DPTF_TSR0_PASSIVE 60
-#define DPTF_TSR0_CRITICAL 105
+#define DPTF_TSR0_PASSIVE 55
+#define DPTF_TSR0_CRITICAL 100
/* Memory Sensor for DDR temperature monitor */
#define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "DDR"
-#define DPTF_TSR1_PASSIVE 70
-#define DPTF_TSR1_CRITICAL 95
+#define DPTF_TSR1_PASSIVE 53
+#define DPTF_TSR1_CRITICAL 100
/* M.2 Sensor for Ambient temperature monitor */
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "Ambient"
-#define DPTF_TSR2_PASSIVE 37
-#define DPTF_TSR2_CRITICAL 80
+#define DPTF_TSR2_PASSIVE 38
+#define DPTF_TSR2_CRITICAL 93
#undef DPTF_ENABLE_FAN_CONTROL
#undef DPTF_ENABLE_CHARGER
@@ -42,10 +42,10 @@
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 500, 30, 0, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 50, 2, 0, 0, 0 },
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 },
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