Attention is currently required from: Shelley Chen, Ravi kumar, Furquan Shaikh, Paul Menzel, Julius Werner, mturney mturney.
3 comments:
File payloads/libpayload/drivers/pci.c:
#if CONFIG(LP_MMCONF_SUPPORT)
void *cfg_addr = lib_sysinfo.pci_ep_cfg_base + reg;
return read8(cfg_addr);
#endif
outl(device | (reg & ~3), 0xCF8);
return inb(0xCFC + (reg & 3));
Just checked patchset#28. I don't think we need to duplicate the entire pci.c file. […]
Hi Furquan,
Thanks for the review.
I have few questions on above context.
Below API's are already present in pci.c file.
pci_io_read_config8
pci_io_write_config8
pci_io_read_config16
pci_io_write_config16
pci_io_read_config32
pci_io_write_config32
are you referring "pci_read/write_config8/16/32" in pci.c file ?
As you mentioned,adding new Kconfig for IO and MMIO. We can add PCI_IO_OPS Kconfig which is default and select for arch_X86.
And new MMIO ops which are added newly in pci_ops.c (patch #28) will be added to the build when MMIO_BASE_ADDRESS is present
Is my analysis is right on above comment ? Please let me know, I will incorporate the changes in next version patch.
Thanks
-Prasad
File payloads/libpayload/drivers/pci_ops.c:
Patch Set #28, Line 37: u32 devfn = ((dev >> 3) & 0x1f) | (dev & 0x07);
I think we are probably going to need separate map functions to map (bus,dev,fn) to the format expec […]
Hi Furquan,
Yes, QC platform required to configure the ATU to access the config space.
In Coreboot PCIe root complex driver, after device enumeration is done we are configuring the ATU for device config access.
we will add the same mapping format which we are using in CB PCIe driver. will validate and incorporate the change in next version.
Thanks
-Prasad
File payloads/libpayload/include/coreboot_tables.h:
Not yet addressed.
Hi Furquan,
I missed it in patch 28 version. Will resolve and incorporate the change in next version.
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