1 comment:
File src/soc/intel/cannonlake/fsp_params.c:
Patch Set #4, Line 410: DevIntConfigPtr
Could you point to some documentation on the format? It's not in coreboot nor in any public FSP inte […]
This UPD holds the pointer to array of SI_PCH_DEVICE_INTERRUPT_CONFIG for PCI IRQ configuration , this struct is documented in integration guide.
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