Felix Singer has uploaded this change for review.
intel skl mainboards: Move PcieRpEnable option below dt entries
There is work being done on better integrating the root port entries
from the devicetree by hooking up the FSP option PcieRpEnable to them,
which supersedes the devicetree option.
Move the PcieRpEnable option below their related devicetree entries in
order to make the review easier when the option is removed.
Change-Id: I397497118d6868e4a6d4086e97901081da7d5fda
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/facebook/monolith/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/fizz/variants/endeavour/overridetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
17 files changed, 202 insertions(+), 135 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79958/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 2695451..1bc6948 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -56,21 +56,18 @@
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# Enable Root Ports 3, 4 and 9
- register "PcieRpEnable[2]" = "1" # Ethernet controller
register "PcieRpClkReqSupport[2]" = "1"
register "PcieRpClkReqNumber[2]" = "0"
register "PcieRpClkSrcNumber[2]" = "0"
register "PcieRpAdvancedErrorReporting[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1" # Wireless controller
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqNumber[3]" = "1"
register "PcieRpClkSrcNumber[3]" = "1"
register "PcieRpAdvancedErrorReporting[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
- register "PcieRpEnable[8]" = "1" # NVMe controller
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "4"
register "PcieRpClkSrcNumber[8]" = "4"
@@ -108,9 +105,18 @@
device ref thermal on end
device ref heci1 on end
device ref sata on end
- device ref pcie_rp3 on end
- device ref pcie_rp4 on end
- device ref pcie_rp9 on end
+ device ref pcie_rp3 on
+ # Ethernet controller
+ register "PcieRpEnable[2]" = "1"
+ end
+ device ref pcie_rp4 on
+ # Wireless controller
+ register "PcieRpEnable[3]" = "1"
+ end
+ device ref pcie_rp9 on
+ # NVMe controller
+ register "PcieRpEnable[8]" = "1"
+ end
device ref lpc_espi on
chip ec/51nb/npce985la0dx
device pnp 0c09.0 on end
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 3f71ca9..e469049 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -136,7 +136,6 @@
# PCIE Port 2 disabled
# PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
- register "PcieRpEnable[2]" = "1"
# Disable CLKREQ#
register "PcieRpClkReqSupport[2]" = "0"
# Set MaxPayload to 256 bytes
@@ -152,7 +151,6 @@
# PCIE Port 5 x1 -> MODULE i219
# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
- register "PcieRpEnable[5]" = "1"
register "PcieRpClkReqSupport[5]" = "0"
# Set MaxPayload to 256 bytes
register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
@@ -167,7 +165,6 @@
# PCIE Port 8 Disabled
# PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
- register "PcieRpEnable[8]" = "1"
# Disable CLKREQ#
register "PcieRpClkReqSupport[8]" = "0"
# Use Hot Plug subsystem
@@ -224,9 +221,18 @@
device ref thermal on end
device ref heci1 on end
device ref sata on end
- device ref pcie_rp3 on end # x1 baseboard WWAN
- device ref pcie_rp6 on end # x1 baseboard i210
- device ref pcie_rp9 on end # x4 FPGA
+ device ref pcie_rp3 on
+ # x1 baseboard WWAN
+ register "PcieRpEnable[2]" = "1"
+ end
+ device ref pcie_rp6 on
+ # x1 baseboard i210
+ register "PcieRpEnable[5]" = "1"
+ end
+ device ref pcie_rp9 on
+ # x4 FPGA
+ register "PcieRpEnable[8]" = "1"
+ end
device ref uart0 on end
device ref emmc on end
device ref lpc_espi on
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index dfa7a6e..d2ffac0 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -126,7 +126,6 @@
}"
# Enable Root port 1 with SRCCLKREQ1#
- register "PcieRpEnable[0]" = "1"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
@@ -136,7 +135,6 @@
register "PcieRpClkSrcNumber[0]" = "1"
# Enable Root port 5 with SRCCLKREQ4#
- register "PcieRpEnable[4]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "4"
register "PcieRpAdvancedErrorReporting[4]" = "1"
@@ -362,12 +360,15 @@
end
end # I2C #4
device ref pcie_rp1 on
+ register "PcieRpEnable[0]" = "1"
chip drivers/wifi/generic
register "wake" = "GPE0_PCI_EXP"
device pci 00.0 on end
end
end
- device ref pcie_rp5 on end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
device ref uart0 on end
device ref gspi0 on
chip drivers/spi/acpi
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 44fc014..b0e2b13 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -159,7 +159,6 @@
}"
# Enable Root port 3(x1) for LAN.
- register "PcieRpEnable[2]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[2]" = "1"
# RP 3 uses SRCCLKREQ0#
@@ -172,7 +171,6 @@
register "PcieRpClkSrcNumber[2]" = "0"
# Enable Root port 4(x1) for WLAN.
- register "PcieRpEnable[3]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[3]" = "1"
# RP 4 uses SRCCLKREQ5#
@@ -185,7 +183,6 @@
register "PcieRpClkSrcNumber[3]" = "5"
# Enable Root port 5(x4) for NVMe.
- register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[4]" = "1"
# RP 5 uses SRCCLKREQ1#
@@ -198,7 +195,6 @@
register "PcieRpClkSrcNumber[4]" = "1"
# Enable Root port 9 for BtoB.
- register "PcieRpEnable[8]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[8]" = "1"
# RP 9 uses SRCCLKREQ2#
@@ -211,7 +207,6 @@
register "PcieRpClkSrcNumber[8]" = "2"
# Enable Root port 11 for BtoB.
- register "PcieRpEnable[10]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[10]" = "1"
# RP 11 uses SRCCLKREQ2#
@@ -224,7 +219,6 @@
register "PcieRpClkSrcNumber[10]" = "2"
# Enable Root port 12 for BtoB.
- register "PcieRpEnable[11]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[11]" = "1"
# RP 12 uses SRCCLKREQ2#
@@ -372,6 +366,7 @@
device ref pcie_rp1 on end
device ref pcie_rp3 on
# LAN, will be swapped to port 1 by FSP
+ register "PcieRpEnable[2]" = "1"
chip drivers/net
register "customized_leds" = "0x0fa5"
register "wake" = "GPE0_PCI_EXP"
@@ -381,22 +376,31 @@
end
device ref pcie_rp4 on
# WLAN
+ register "PcieRpEnable[3]" = "1"
chip drivers/wifi/generic
register "wake" = "GPE0_PCI_EXP"
device pci 00.0 on end
end
end
- device ref pcie_rp5 on end # NVMe
+ device ref pcie_rp5 on
+ # NVMe
+ register "PcieRpEnable[4]" = "1"
+ end
device ref pcie_rp9 on
# 2nd LAN
+ register "PcieRpEnable[8]" = "1"
chip drivers/net
register "customized_leds" = "0x0fa5"
register "device_index" = "1"
device pci 00.0 on end
end
end
- device ref pcie_rp11 on end
- device ref pcie_rp12 on end
+ device ref pcie_rp11 on
+ register "PcieRpEnable[10]" = "1"
+ end
+ device ref pcie_rp12 on
+ register "PcieRpEnable[11]" = "1"
+ end
device ref uart0 on end
device ref gspi0 on
chip drivers/spi/acpi
diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 989b2406..685f2fc 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -1,7 +1,6 @@
chip soc/intel/skylake
# Enable Root port 7(x1) for TPU1
- register "PcieRpEnable[6]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[6]" = "1"
# RP 7 uses SRCCLKREQ4#
@@ -14,7 +13,6 @@
register "PcieRpClkSrcNumber[6]" = "4"
# Enable Root port 8(x1) for TPU0
- register "PcieRpEnable[7]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[7]" = "1"
# RP 8 uses SRCCLKREQ2#
@@ -27,7 +25,6 @@
register "PcieRpClkSrcNumber[7]" = "2"
# Enable Root port 9(x4) for i350 LAN
- register "PcieRpEnable[8]" = "1"
# Disable CLKREQ#
register "PcieRpClkReqSupport[8]" = "0"
# RP 9, Enable Advanced Error Reporting
@@ -37,11 +34,6 @@
# RP 9 uses CLK SRC 2
register "PcieRpClkSrcNumber[8]" = "2"
- # These are part of Root port 9(x4)
- register "PcieRpEnable[9]" = "0"
- register "PcieRpEnable[10]" = "0"
- register "PcieRpEnable[11]" = "0"
-
register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # HDMI
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Rear
@@ -156,11 +148,17 @@
device i2c 13 on end
end
end
- device ref pcie_rp7 on end # TPU1
- device ref pcie_rp8 on end # TPU0
- device ref pcie_rp9 on end # POE LAN
- device ref pcie_rp10 off end
- device ref pcie_rp11 off end
- device ref pcie_rp12 off end
+ device ref pcie_rp7 on
+ # TPU1
+ register "PcieRpEnable[6]" = "1"
+ end
+ device ref pcie_rp8 on
+ # TPU0
+ register "PcieRpEnable[7]" = "1"
+ end
+ device ref pcie_rp9 on
+ # POE LAN
+ register "PcieRpEnable[8]" = "1"
+ end
end
end
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 58b421c..b254fe8 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -49,7 +49,6 @@
register "PmConfigSlpAMinAssert" = "3" # 2s
# Enable Root port 1
- register "PcieRpEnable[0]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[0]" = "1"
# RP 1 uses SRCCLKREQ1#
@@ -93,6 +92,7 @@
device ref uart2 on end
device ref i2c4 on end
device ref pcie_rp1 on
+ register "PcieRpEnable[0]" = "1"
chip drivers/wifi/generic
register "wake" = "GPE0_DW0_16"
device pci 00.0 on end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index b580e76..04024cb 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -6,38 +6,31 @@
register "serirq_mode" = "SERIRQ_CONTINUOUS"
- # Enable PCIE slot
- register "PcieRpEnable[5]" = "1"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "1" #uses SRCCLKREQ1
# RP6, uses CLK SRC 1
register "PcieRpClkSrcNumber[5]" = "1"
- register "PcieRpEnable[6]" = "1"
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "2" #uses SRCCLKREQ2
# RP7, uses CLK SRC 2
register "PcieRpClkSrcNumber[6]" = "2"
- register "PcieRpEnable[7]" = "1"
register "PcieRpClkReqSupport[7]" = "1"
register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
# RP8, uses CLK SRC 3
register "PcieRpClkSrcNumber[7]" = "3"
- register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
# RP9, uses CLK SRC 4
register "PcieRpClkSrcNumber[8]" = "4"
- register "PcieRpEnable[13]" = "1"
register "PcieRpClkReqSupport[13]" = "1"
register "PcieRpClkReqNumber[13]" = "5" #uses SRCCLKREQ5
# RP14, uses CLK SRC 5
register "PcieRpClkSrcNumber[13]" = "5"
- register "PcieRpEnable[16]" = "1"
register "PcieRpClkReqSupport[16]" = "1"
register "PcieRpClkReqNumber[16]" = "7" #uses SRCCLKREQ7
# RP17, uses CLK SRC 7
@@ -116,5 +109,23 @@
device ref sdxc off end
device ref hda on end
device ref gbe on end
+ device ref pcie_rp6 on
+ register "PcieRpEnable[5]" = "1"
+ end
+ device ref pcie_rp7 on
+ register "PcieRpEnable[6]" = "1"
+ end
+ device ref pcie_rp8 on
+ register "PcieRpEnable[7]" = "1"
+ end
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ end
+ device ref pcie_rp14 on
+ register "PcieRpEnable[13]" = "1"
+ end
+ device ref pcie_rp17 on
+ register "PcieRpEnable[16]" = "1"
+ end
end
end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index b7c4395..b3668b9 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -38,21 +38,18 @@
# Enable Root ports.
# PCIE Port 1 x4 -> SLOT1
- register "PcieRpEnable[0]" = "1"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "2"
# RP1, uses CLK SRC 2
register "PcieRpClkSrcNumber[0]" = "2"
# PCIE Port 5 x1 -> SLOT2/LAN
- register "PcieRpEnable[4]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "3"
# RP5, uses CLK SRC 3
register "PcieRpClkSrcNumber[4]" = "3"
# PCIE Port 6 x1 -> SLOT3
- register "PcieRpEnable[5]" = "1"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "1"
# RP6, uses CLK SRC 1
@@ -61,14 +58,12 @@
# PCIE Port 7 Disabled
# PCIE Port 8 Disabled
# PCIE Port 9 x1 -> WLAN
- register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "5"
# RP9, uses CLK SRC 5
register "PcieRpClkSrcNumber[8]" = "5"
# PCIE Port 10 x1 -> WiGig
- register "PcieRpEnable[9]" = "1"
register "PcieRpClkReqSupport[9]" = "1"
register "PcieRpClkReqNumber[9]" = "4"
# RP10, uses CLK SRC 4
@@ -115,11 +110,26 @@
device domain 0 on
device ref imgu on end
device ref cio on end
- device ref pcie_rp1 on end # x4 SLOT1
- device ref pcie_rp5 on end # x1 SLOT2/LAN
- device ref pcie_rp6 on end # x1 SLOT3
- device ref pcie_rp9 on end # x1 WLAN
- device ref pcie_rp10 on end # x1 WIGIG
+ device ref pcie_rp1 on
+ # x4 SLOT1
+ register "PcieRpEnable[0]" = "1"
+ end
+ device ref pcie_rp5 on
+ # x1 SLOT2/LAN
+ register "PcieRpEnable[4]" = "1"
+ end
+ device ref pcie_rp6 on
+ # x1 SLOT3
+ register "PcieRpEnable[5]" = "1"
+ end
+ device ref pcie_rp9 on
+ # x1 WLAN
+ register "PcieRpEnable[8]" = "1"
+ end
+ device ref pcie_rp10 on
+ # x1 WIGIG
+ register "PcieRpEnable[9]" = "1"
+ end
device ref lpc_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index c5b7e94..1d32850 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -81,13 +81,6 @@
.voltage_limit = 0
}"
- # Enable Root ports.
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "1"
- register "PcieRpEnable[8]" = "1"
-
# Enable CLKREQ#
register "PcieRpClkReqSupport[2]" = "1"
register "PcieRpClkReqSupport[3]" = "1"
@@ -158,10 +151,21 @@
device ref i2c2 off end
device ref i2c3 off end
device ref sata on end
- device ref pcie_rp3 on end
- device ref pcie_rp4 on end
- device ref pcie_rp5 on end
- device ref pcie_rp6 on end
+ device ref pcie_rp3 on
+ register "PcieRpEnable[2]" = "1"
+ end
+ device ref pcie_rp4 on
+ register "PcieRpEnable[3]" = "1"
+ end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
+ device ref pcie_rp6 on
+ register "PcieRpEnable[5]" = "1"
+ end
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ end
device ref lpc_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 2291c63..df5e62e 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -77,11 +77,6 @@
.voltage_limit = 0
}"
- # Enable Root port.
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[16]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[3]" = "1"
@@ -166,8 +161,18 @@
device ref i2c4 off end
device ref pcie_rp1 off end
device ref pcie_rp3 on end
- device ref pcie_rp4 on end
- device ref pcie_rp5 on end
+ device ref pcie_rp4 on
+ register "PcieRpEnable[3]" = "1"
+ end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ end
+ device ref pcie_rp17 on
+ register "PcieRpEnable[16]" = "1"
+ end
device ref emmc off end
device ref sdxc off end
device ref lpc_espi on
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 0d9331b..71576b7 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -108,8 +108,6 @@
}"
# Enable Root port 1 and 5.
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[4]" = "1"
# Enable CLKREQ#
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqSupport[4]" = "1"
@@ -225,12 +223,15 @@
end
end
device ref pcie_rp1 on
+ register "PcieRpEnable[0]" = "1"
chip drivers/wifi/generic
register "wake" = "GPE0_DW0_16"
device pci 00.0 on end
end
end
- device ref pcie_rp5 on end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
device ref uart0 on end
device ref emmc on end
device ref sdxc on end
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index f2234a6..bba3ce8 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -102,19 +102,13 @@
}"
# Enable x1 slot
- register "PcieRpEnable[7]" = "1"
register "PcieRpClkReqSupport[7]" = "1"
register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
# Enable x4 slot
- register "PcieRpEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
- # Enable Root port 6 and 13.
- register "PcieRpEnable[5]" = "1"
- register "PcieRpEnable[12]" = "1"
-
# Enable CLKREQ#
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqSupport[12]" = "1"
@@ -211,6 +205,18 @@
device ref i2c5 on end
device ref i2c4 on end
device ref pcie_rp1 on end
+ device ref pcie_rp6 on
+ register "PcieRpEnable[5]" = "1"
+ end
+ device ref pcie_rp8 on
+ register "PcieRpEnable[7]" = "1"
+ end
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ end
+ device ref pcie_rp13 on
+ register "PcieRpEnable[12]" = "1"
+ end
device ref uart0 on end
device ref uart1 on end
device ref gspi0 on end
diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
index ecfcd6f..89c86d4 100644
--- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
+++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
@@ -1,13 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/skylake
- # Enable Root port 1..4 (COMe 4..7), 12 (COMe 3)
- register "PcieRpEnable[ 0]" = "1"
- register "PcieRpEnable[ 1]" = "1"
- register "PcieRpEnable[ 2]" = "1"
- register "PcieRpEnable[ 3]" = "1"
- register "PcieRpEnable[11]" = "1"
-
register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)"
register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)"
register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)"
@@ -21,11 +14,21 @@
register "SataPortsEnable[3]" = "1"
device domain 0 on
- device ref pcie_rp1 on end
- device ref pcie_rp2 on end
- device ref pcie_rp3 on end
- device ref pcie_rp4 on end
- device ref pcie_rp12 on end
+ device ref pcie_rp1 on
+ register "PcieRpEnable[0]" = "1"
+ end
+ device ref pcie_rp2 on
+ register "PcieRpEnable[1]" = "1"
+ end
+ device ref pcie_rp3 on
+ register "PcieRpEnable[2]" = "1"
+ end
+ device ref pcie_rp4 on
+ register "PcieRpEnable[3]" = "1"
+ end
+ device ref pcie_rp12 on
+ register "PcieRpEnable[11]" = "1"
+ end
device ref smbus on
chip drivers/i2c/nct7802y
register "peci[0]" = "{ PECI_DOMAIN_0, 100 }"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index cdddf3d..ef3ec23 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -117,13 +117,6 @@
.voltage_limit = 1520,
}"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[8]" = "1"
- register "PcieRpEnable[9]" = "1"
- register "PcieRpEnable[10]" = "1"
- register "PcieRpEnable[11]" = "1"
register "PcieRpClkSrcNumber[0]" = "0"
register "PcieRpClkSrcNumber[3]" = "1"
@@ -168,19 +161,32 @@
device ref thermal on end
device ref heci1 on end
device ref sata on end
- device ref pcie_rp3 on end
+ device ref pcie_rp3 on
+ register "PcieRpEnable[2]" = "1"
+ end
+ device ref pcie_rp4 on
+ register "PcieRpEnable[3]" = "1"
+ end
device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO"
"SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X"
end
device ref pcie_rp6 on end
device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"SSD_M.2 2242/2280" "SlotDataBusWidth4X"
end
- device ref pcie_rp10 on end
- device ref pcie_rp11 on end
- device ref pcie_rp12 on end
+ device ref pcie_rp10 on
+ register "PcieRpEnable[9]" = "1"
+ end
+ device ref pcie_rp11 on
+ register "PcieRpEnable[10]" = "1"
+ end
+ device ref pcie_rp12 on
+ register "PcieRpEnable[11]" = "1"
+ end
device ref lpc_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 092115c..7d95eaa 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -116,15 +116,6 @@
register "SataPortsDevSlp[0]" = "0"
register "SataPortsDevSlp[1]" = "0"
- # Enable Root ports. 1-6 for LAN and Root Port 9
- register "PcieRpEnable[0]" = "1"
- register "PcieRpEnable[1]" = "1"
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[3]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[5]" = "1"
- register "PcieRpEnable[8]" = "1" # mPCIe WiFi
-
# Enable Advanced Error Reporting for RP 1-6, 9
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpAdvancedErrorReporting[1]" = "1"
@@ -158,7 +149,6 @@
# RP 9 shares CLKSRC5# with RP 6
register "PcieRpClkSrcNumber[8]" = "5"
-
# USB 2.0 enable ports 1-8, disable ports 9-12
register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port
@@ -195,14 +185,27 @@
device ref south_xhci on end
device ref heci1 on end
device ref sata on end
- device ref pcie_rp1 on end
- device ref pcie_rp2 on end
- device ref pcie_rp3 on end
- device ref pcie_rp4 on end
- device ref pcie_rp5 on end
- device ref pcie_rp6 on end
+ device ref pcie_rp1 on
+ register "PcieRpEnable[0]" = "1"
+ end
+ device ref pcie_rp2 on
+ register "PcieRpEnable[1]" = "1"
+ end
+ device ref pcie_rp3 on
+ register "PcieRpEnable[2]" = "1"
+ end
+ device ref pcie_rp4 on
+ register "PcieRpEnable[3]" = "1"
+ end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
+ device ref pcie_rp6 on
+ register "PcieRpEnable[5]" = "1"
+ end
device ref pcie_rp9 on
- # WIFI
+ # mPCIe WIFI
+ register "PcieRpEnable[8]" = "1"
smbios_slot_desc
"SlotTypePciExpressMini52pinWithoutBSKO"
"SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 1928d15..7cfa675 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -137,10 +137,6 @@
.dc_loadline = 420,
}"
- # Enable Root Ports 5 and 9
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[8]" = "1"
-
# PL2 override 25W
register "power_limits_config" = "{
.tdp_pl2_override = 25,
@@ -158,7 +154,12 @@
device ref thermal on end
device ref sata on end
device ref pcie_rp1 on end
- device ref pcie_rp9 on end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ end
device ref lpc_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 1323164..2545dc5 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -115,11 +115,6 @@
.dc_loadline = 310,
}"
- # Enable Root Ports 3, 5 and 9
- register "PcieRpEnable[2]" = "1"
- register "PcieRpEnable[4]" = "1"
- register "PcieRpEnable[8]" = "1"
-
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpLtrEnable[8]" = "1"
@@ -188,8 +183,15 @@
device ref heci1 on end
device ref uart2 on end
device ref pcie_rp1 on end
- device ref pcie_rp5 on end
- device ref pcie_rp9 on end
+ device ref pcie_rp3 on
+ register "PcieRpEnable[2]" = "1"
+ end
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ end
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ end
device ref lpc_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
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