Jes Klinke would like Jes Klinke to review this change.

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soc/intel/common/block/gspi: Recalculate BAR after resource allocation

The base address of the memory mapped I/O registers should not
be cached across resource allocation.  This CL will evict the cached
value upon exiting the BS_DEV_RESOURCES stage.

Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821
Signed-off-by: jbk@chromium.org
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44084/1

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 599ab7e..6337226 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -2,6 +2,7 @@
 
 #include <device/mmio.h>
 #include <assert.h>
+#include <bootstate.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
@@ -257,6 +258,12 @@
 	return gspi_base[gspi_bus];
 }
 
+static void gspi_clear_base_stash(void *unused)
+{
+	memset(gspi_base, 0, sizeof(gspi_base));
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_base_stash, NULL);
+
 /* Parameters for GSPI controller operation. */
 struct gspi_ctrlr_params {
 	uintptr_t mmio_base;

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