[coreboot-gerrit] Patch set updated for coreboot: c9e3642 google/panther: Use ISO C99 syntax for designated initializers

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6024

-gerrit

commit c9e3642780cd78a105bd611a244b4e923e6b4d21
Author: Matt DeVillier 
Date:   Thu Jun 12 12:21:07 2014 -0500

google/panther: Use ISO C99 syntax for designated initializers

In C99 we defined a syntax for this. GCC’s old syntax is deprecated.

Modelled after commit 8089f178 (mainboard/lenovo/x230 Fix usage of GNU field
    designator extension) [1].

[1] http://review.coreboot.org/5392

Change-Id: I51c72252800be64b9420d845e330fc0481c66470
    Signed-off-by: Matt DeVillier 
---
 src/mainboard/google/panther/romstage.c | 50 ++++++++++++++++-----------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c
index 3496b53..c367968 100644
--- a/src/mainboard/google/panther/romstage.c
+++ b/src/mainboard/google/panther/romstage.c
@@ -80,35 +80,35 @@ const struct rcba_config_instruction rcba_config[] = {
 void mainboard_romstage_entry(unsigned long bist)
 {
    struct pei_data pei_data = {
-		pei_version: PEI_VERSION,
-		mchbar: DEFAULT_MCHBAR,
-		dmibar: DEFAULT_DMIBAR,
-		epbar: DEFAULT_EPBAR,
-		pciexbar: DEFAULT_PCIEXBAR,
-		smbusbar: SMBUS_IO_BASE,
-		wdbbar: 0x4000000,
-		wdbsize: 0x1000,
-		hpet_address: HPET_ADDR,
-		rcba: DEFAULT_RCBA,
-		pmbase: DEFAULT_PMBASE,
-		gpiobase: DEFAULT_GPIOBASE,
-		temp_mmio_base: 0xfed08000,
-		system_type: 5, /* ULT */
-		tseg_size: CONFIG_SMM_TSEG_SIZE,
-		spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 },
-		ec_present: 0,
+		.pei_version = PEI_VERSION,
+		.mchbar = DEFAULT_MCHBAR,
+		.dmibar = DEFAULT_DMIBAR,
+		.epbar = DEFAULT_EPBAR,
+		.pciexbar = DEFAULT_PCIEXBAR,
+		.smbusbar = SMBUS_IO_BASE,
+		.wdbbar = 0x4000000,
+		.wdbsize = 0x1000,
+		.hpet_address = HPET_ADDR,
+		.rcba = DEFAULT_RCBA,
+		.pmbase = DEFAULT_PMBASE,
+		.gpiobase = DEFAULT_GPIOBASE,
+		.temp_mmio_base = 0xfed08000,
+		.system_type = 5, /* ULT */
+		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
+		.ec_present = 0,
    	// 0 = leave channel enabled
    	// 1 = disable dimm 0 on channel
    	// 2 = disable dimm 1 on channel
    	// 3 = disable dimm 0+1 on channel
-		dimm_channel0_disabled: 2,
-		dimm_channel1_disabled: 2,
+		.dimm_channel0_disabled = 2,
+		.dimm_channel1_disabled = 2,
    	// Enable 2x refresh mode
-		ddr_refresh_2x: 1,
-		dq_pins_interleaved: 1,
-		max_ddr3_freq: 1600,
-		usb_xhci_on_resume: 1,
-		usb2_ports: {
+		.ddr_refresh_2x = 1,
+		.dq_pins_interleaved = 1,
+		.max_ddr3_freq = 1600,
+		.usb_xhci_on_resume = 1,
+		.usb2_ports = {
    		/* Length, Enable, OCn#, Location */
    		{ 0x0064, 1, 0,               /* P0: VP8 */
    		  USB_PORT_MINI_PCIE },
@@ -127,7 +127,7 @@ void mainboard_romstage_entry(unsigned long bist)
    		{ 0x0000, 0, 0,               /* P7: N/C */
    		  USB_PORT_SKIP },
    	},
-		usb3_ports: {
+		.usb3_ports = {
    		/* Enable, OCn# */
    		{ 1, 0 }, /* P1; CN22 */
    		{ 1, 1 }, /* P2; CN23  */