Attention is currently required from: Philipp Hug, ron minnich.
Martin L Roth has uploaded this change for review.
arch/riscv: Reformat C files with clang-format v16
Reformat only - No functional changes.
Change-Id: Ic863ec7e56f86da7f1967ac4c566bb988071d127
Signed-off-by: Martin Roth <gaumless@gmail.com>
---
M src/arch/riscv/boot.c
M src/arch/riscv/fit_payload.c
M src/arch/riscv/misaligned.c
M src/arch/riscv/opensbi.c
M src/arch/riscv/payload.c
M src/arch/riscv/pmp.c
M src/arch/riscv/smp.c
M src/arch/riscv/tables.c
M src/arch/riscv/trap_handler.c
M src/arch/riscv/virtual_memory.c
10 files changed, 97 insertions(+), 122 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/80011/1
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index a59f9d1..bf2056c 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -51,7 +51,7 @@
/* In case of OpenSBI we have to load it before resuming all HARTs */
if (ENV_RAMSTAGE && CONFIG(RISCV_OPENSBI)) {
- struct prog sbi = PROG_INIT(PROG_OPENSBI, CONFIG_CBFS_PREFIX"/opensbi");
+ struct prog sbi = PROG_INIT(PROG_OPENSBI, CONFIG_CBFS_PREFIX "/opensbi");
if (!selfload_check(&sbi, BM_MEM_OPENSBI))
die("OpenSBI load failed");
diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c
index bfa0c98..24d80ee 100644
--- a/src/arch/riscv/fit_payload.c
+++ b/src/arch/riscv/fit_payload.c
@@ -9,7 +9,7 @@
/* Implements a Berkeley Boot Loader (BBL) compatible payload loading */
-#define MAX_KERNEL_SIZE (64*MiB)
+#define MAX_KERNEL_SIZE (64 * MiB)
#if CONFIG(ARCH_RISCV_RV32)
#define SECTION_ALIGN (4 * MiB)
@@ -28,8 +28,7 @@
* effectively unbound.
*/
- printk(BIOS_INFO,
- "FIT: Leaving additional %u MiB of free space after kernel.\n",
+ printk(BIOS_INFO, "FIT: Leaving additional %u MiB of free space after kernel.\n",
MAX_KERNEL_SIZE >> 20);
return node->size + MAX_KERNEL_SIZE;
@@ -60,23 +59,20 @@
}
bool fit_payload_arch(struct prog *payload, struct fit_config_node *config,
- struct region *kernel,
- struct region *fdt,
- struct region *initrd)
+ struct region *kernel, struct region *fdt, struct region *initrd)
{
void *arg = NULL;
if (!config->fdt || !fdt) {
printk(BIOS_CRIT, "Providing a valid FDT is mandatory to "
- "boot a RISC-V kernel!\n");
+ "boot a RISC-V kernel!\n");
return false;
/* TODO: Fall back to the ROM FDT? */
}
/* Update kernel size from image header, if possible */
kernel->size = get_kernel_size(config->kernel);
- printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n",
- kernel->size);
+ printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n", kernel->size);
/*
* The code assumes that bootmem_walk provides a sorted list of memory
diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c
index 9f144b8..6ab712b7 100644
--- a/src/arch/riscv/misaligned.c
+++ b/src/arch/riscv/misaligned.c
@@ -8,21 +8,21 @@
/* these functions are defined in src/arch/riscv/fp_asm.S */
#if defined(__riscv_flen)
#if __riscv_flen >= 32
-extern void read_f32(int regnum, uint32_t *v);
+extern void read_f32(int regnum, uint32_t *v);
extern void write_f32(int regnum, uint32_t *v);
#endif // __riscv_flen >= 32
#if __riscv_flen >= 64
-extern void read_f64(int regnum, uint64_t *v);
+extern void read_f64(int regnum, uint64_t *v);
extern void write_f64(int regnum, uint64_t *v);
#endif // __riscv_flen >= 64
#endif // defined(__riscv_flen)
/* This union makes it easy to read multibyte types by byte operations. */
union endian_buf {
- uint8_t b[8];
- uint16_t h[4];
- uint32_t w[2];
- uint64_t d[1];
+ uint8_t b[8];
+ uint16_t h[4];
+ uint32_t w[2];
+ uint64_t d[1];
uintptr_t v;
};
@@ -37,89 +37,89 @@
unsigned int reg_shift;
unsigned int reg_mask;
unsigned int reg_addition;
- unsigned int is_fp : 1; /* mark as a float operation */
- unsigned int is_load : 1; /* mark as a load operation */
- unsigned int width : 8; /* Record the memory width of the operation */
+ unsigned int is_fp : 1; /* mark as a float operation */
+ unsigned int is_load : 1; /* mark as a load operation */
+ unsigned int width : 8; /* Record the memory width of the operation */
unsigned int sign_extend : 1; /* mark need to be sign extended */
};
static struct memory_instruction_info insn_info[] = {
#if __riscv_xlen == 128
- { 0x00002000, 0x0000e003, 2, 7, 8, 0, 1, 16, 1}, // C.LQ
+ {0x00002000, 0x0000e003, 2, 7, 8, 0, 1, 16, 1}, // C.LQ
#else
- { 0x00002000, 0x0000e003, 2, 7, 8, 1, 1, 8, 0}, // C.FLD
+ {0x00002000, 0x0000e003, 2, 7, 8, 1, 1, 8, 0}, // C.FLD
#endif
- { 0x00004000, 0x0000e003, 2, 7, 8, 0, 1, 4, 1}, // C.LW
+ {0x00004000, 0x0000e003, 2, 7, 8, 0, 1, 4, 1}, // C.LW
#if __riscv_xlen == 32
- { 0x00006000, 0x0000e003, 2, 7, 8, 1, 1, 4, 0}, // C.FLW
+ {0x00006000, 0x0000e003, 2, 7, 8, 1, 1, 4, 0}, // C.FLW
#else
- { 0x00006000, 0x0000e003, 2, 7, 8, 0, 1, 8, 1}, // C.LD
+ {0x00006000, 0x0000e003, 2, 7, 8, 0, 1, 8, 1}, // C.LD
#endif
#if __riscv_xlen == 128
- { 0x0000a000, 0x0000e003, 2, 7, 8, 0, 0, 16, 0}, // C.SQ
+ {0x0000a000, 0x0000e003, 2, 7, 8, 0, 0, 16, 0}, // C.SQ
#else
- { 0x0000a000, 0x0000e003, 2, 7, 8, 1, 0, 8, 0}, // C.FSD
+ {0x0000a000, 0x0000e003, 2, 7, 8, 1, 0, 8, 0}, // C.FSD
#endif
- { 0x0000c000, 0x0000e003, 2, 7, 8, 0, 0, 4, 0}, // C.SW
+ {0x0000c000, 0x0000e003, 2, 7, 8, 0, 0, 4, 0}, // C.SW
#if __riscv_xlen == 32
- { 0x0000e000, 0x0000e003, 2, 7, 8, 1, 0, 4, 0}, // C.FSW
+ {0x0000e000, 0x0000e003, 2, 7, 8, 1, 0, 4, 0}, // C.FSW
#else
- { 0x0000e000, 0x0000e003, 2, 7, 8, 0, 0, 8, 0}, // C.SD
+ {0x0000e000, 0x0000e003, 2, 7, 8, 0, 0, 8, 0}, // C.SD
#endif
#if __riscv_xlen == 128
- { 0x00002002, 0x0000e003, 7, 15, 0, 0, 1, 16, 1}, // C.LQSP
+ {0x00002002, 0x0000e003, 7, 15, 0, 0, 1, 16, 1}, // C.LQSP
#else
- { 0x00002002, 0x0000e003, 7, 15, 0, 1, 1, 8, 0}, // C.FLDSP
+ {0x00002002, 0x0000e003, 7, 15, 0, 1, 1, 8, 0}, // C.FLDSP
#endif
- { 0x00004002, 0x0000e003, 7, 15, 0, 0, 1, 4, 1}, // C.LWSP
+ {0x00004002, 0x0000e003, 7, 15, 0, 0, 1, 4, 1}, // C.LWSP
#if __riscv_xlen == 32
- { 0x00006002, 0x0000e003, 7, 15, 0, 1, 1, 4, 0}, // C.FLWSP
+ {0x00006002, 0x0000e003, 7, 15, 0, 1, 1, 4, 0}, // C.FLWSP
#else
- { 0x00006002, 0x0000e003, 7, 15, 0, 0, 1, 8, 1}, // C.LDSP
+ {0x00006002, 0x0000e003, 7, 15, 0, 0, 1, 8, 1}, // C.LDSP
#endif
#if __riscv_xlen == 128
- { 0x0000a002, 0x0000e003, 2, 15, 0, 0, 0, 16, 0}, // C.SQSP
+ {0x0000a002, 0x0000e003, 2, 15, 0, 0, 0, 16, 0}, // C.SQSP
#else
- { 0x0000a002, 0x0000e003, 2, 15, 0, 1, 0, 8, 0}, // C.FSDSP
+ {0x0000a002, 0x0000e003, 2, 15, 0, 1, 0, 8, 0}, // C.FSDSP
#endif
- { 0x0000c002, 0x0000e003, 2, 15, 0, 0, 0, 4, 0}, // C.SWSP
+ {0x0000c002, 0x0000e003, 2, 15, 0, 0, 0, 4, 0}, // C.SWSP
#if __riscv_xlen == 32
- { 0x0000e002, 0x0000e003, 2, 15, 0, 1, 0, 4, 0}, // C.FSWSP
+ {0x0000e002, 0x0000e003, 2, 15, 0, 1, 0, 4, 0}, // C.FSWSP
#else
- { 0x0000e002, 0x0000e003, 2, 15, 0, 0, 0, 8, 0}, // C.SDSP
+ {0x0000e002, 0x0000e003, 2, 15, 0, 0, 0, 8, 0}, // C.SDSP
#endif
- { 0x00000003, 0x0000707f, 7, 15, 0, 0, 1, 1, 1}, // LB
- { 0x00001003, 0x0000707f, 7, 15, 0, 0, 1, 2, 1}, // LH
- { 0x00002003, 0x0000707f, 7, 15, 0, 0, 1, 4, 1}, // LW
+ {0x00000003, 0x0000707f, 7, 15, 0, 0, 1, 1, 1}, // LB
+ {0x00001003, 0x0000707f, 7, 15, 0, 0, 1, 2, 1}, // LH
+ {0x00002003, 0x0000707f, 7, 15, 0, 0, 1, 4, 1}, // LW
#if __riscv_xlen > 32
- { 0x00003003, 0x0000707f, 7, 15, 0, 0, 1, 8, 1}, // LD
+ {0x00003003, 0x0000707f, 7, 15, 0, 0, 1, 8, 1}, // LD
#endif
- { 0x00004003, 0x0000707f, 7, 15, 0, 0, 1, 1, 0}, // LBU
- { 0x00005003, 0x0000707f, 7, 15, 0, 0, 1, 2, 0}, // LHU
- { 0x00006003, 0x0000707f, 7, 15, 0, 0, 1, 4, 0}, // LWU
+ {0x00004003, 0x0000707f, 7, 15, 0, 0, 1, 1, 0}, // LBU
+ {0x00005003, 0x0000707f, 7, 15, 0, 0, 1, 2, 0}, // LHU
+ {0x00006003, 0x0000707f, 7, 15, 0, 0, 1, 4, 0}, // LWU
- { 0x00000023, 0x0000707f, 20, 15, 0, 0, 0, 1, 0}, // SB
- { 0x00001023, 0x0000707f, 20, 15, 0, 0, 0, 2, 0}, // SH
- { 0x00002023, 0x0000707f, 20, 15, 0, 0, 0, 4, 0}, // SW
+ {0x00000023, 0x0000707f, 20, 15, 0, 0, 0, 1, 0}, // SB
+ {0x00001023, 0x0000707f, 20, 15, 0, 0, 0, 2, 0}, // SH
+ {0x00002023, 0x0000707f, 20, 15, 0, 0, 0, 4, 0}, // SW
#if __riscv_xlen > 32
- { 0x00003023, 0x0000707f, 20, 15, 0, 0, 0, 8, 0}, // SD
+ {0x00003023, 0x0000707f, 20, 15, 0, 0, 0, 8, 0}, // SD
#endif
#if defined(__riscv_flen)
#if __riscv_flen >= 32
- { 0x00002007, 0x0000707f, 7, 15, 0, 1, 1, 4, 0}, // FLW
- { 0x00003007, 0x0000707f, 7, 15, 0, 1, 1, 8, 0}, // FLD
-#endif // __riscv_flen >= 32
+ {0x00002007, 0x0000707f, 7, 15, 0, 1, 1, 4, 0}, // FLW
+ {0x00003007, 0x0000707f, 7, 15, 0, 1, 1, 8, 0}, // FLD
+#endif // __riscv_flen >= 32
#if __riscv_flen >= 64
- { 0x00002027, 0x0000707f, 20, 15, 0, 1, 0, 4, 0}, // FSW
- { 0x00003027, 0x0000707f, 20, 15, 0, 1, 0, 8, 0}, // FSD
-#endif // __riscv_flen >= 64
-#endif // defined(__riscv_flen)
+ {0x00002027, 0x0000707f, 20, 15, 0, 1, 0, 4, 0}, // FSW
+ {0x00003027, 0x0000707f, 20, 15, 0, 1, 0, 8, 0}, // FSD
+#endif // __riscv_flen >= 64
+#endif // defined(__riscv_flen)
};
static struct memory_instruction_info *match_instruction(uintptr_t insn)
@@ -147,8 +147,7 @@
uint32_t l = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 0);
uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 1);
uint32_t ins = (h << 16) | l;
- if ((EXTRACT_FIELD(ins, 0x3) == 3) &&
- (EXTRACT_FIELD(ins, 0x1c) != 0x7)) {
+ if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) {
*insn = ins;
*size = 4;
return CB_SUCCESS;
diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c
index 48f0f2a..1d79625 100644
--- a/src/arch/riscv/opensbi.c
+++ b/src/arch/riscv/opensbi.c
@@ -9,10 +9,7 @@
#include <arch/boot.h>
/* DO NOT INCLUDE COREBOOT HEADERS HERE */
-void run_opensbi(const int hart_id,
- const void *fdt,
- const void *opensbi,
- const void *payload,
+void run_opensbi(const int hart_id, const void *fdt, const void *opensbi, const void *payload,
const int payload_mode)
{
struct fw_dynamic_info info = {
@@ -23,11 +20,11 @@
};
csr_write(mepc, opensbi);
- asm volatile (
- "mv a0, %0\n\t"
- "mv a1, %1\n\t"
- "mv a2, %2\n\t"
- "mret" :
- : "r"(hart_id), "r"(fdt), "r"(&info)
- : "a0", "a1", "a2");
+ asm volatile("mv a0, %0\n\t"
+ "mv a1, %1\n\t"
+ "mv a2, %2\n\t"
+ "mret"
+ :
+ : "r"(hart_id), "r"(fdt), "r"(&info)
+ : "a0", "a1", "a2");
}
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index ee2ee8e..8db6f2a 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -61,10 +61,9 @@
}
write_csr(mstatus, status);
write_csr(mepc, doit);
- asm volatile(
- "mv a0, %0\n\t"
- "mv a1, %1\n\t"
- "mret" ::"r"(hart_id),
- "r"(fdt)
- : "a0", "a1");
+ asm volatile("mv a0, %0\n\t"
+ "mv a1, %1\n\t"
+ "mret" ::"r"(hart_id),
+ "r"(fdt)
+ : "a0", "a1");
}
diff --git a/src/arch/riscv/pmp.c b/src/arch/riscv/pmp.c
index ee39ac4..1578ab5 100644
--- a/src/arch/riscv/pmp.c
+++ b/src/arch/riscv/pmp.c
@@ -6,7 +6,7 @@
#include <console/console.h>
#include <commonlib/helpers.h>
-#define GRANULE (1 << PMP_SHIFT)
+#define GRANULE (1 << PMP_SHIFT)
/*
* This structure is used to temporarily record PMP
@@ -65,26 +65,22 @@
switch (idx >> 2) {
case 0:
old = read_csr(pmpcfg0);
- new = (old & ~((uintptr_t)0xff << shift))
- | ((cfg & 0xff) << shift);
+ new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift);
write_csr(pmpcfg0, new);
break;
case 1:
old = read_csr(pmpcfg1);
- new = (old & ~((uintptr_t)0xff << shift))
- | ((cfg & 0xff) << shift);
+ new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift);
write_csr(pmpcfg1, new);
break;
case 2:
old = read_csr(pmpcfg2);
- new = (old & ~((uintptr_t)0xff << shift))
- | ((cfg & 0xff) << shift);
+ new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift);
write_csr(pmpcfg2, new);
break;
case 3:
old = read_csr(pmpcfg3);
- new = (old & ~((uintptr_t)0xff << shift))
- | ((cfg & 0xff) << shift);
+ new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift);
write_csr(pmpcfg3, new);
break;
}
@@ -93,14 +89,12 @@
switch (idx >> 3) {
case 0:
old = read_csr(pmpcfg0);
- new = (old & ~((uintptr_t)0xff << shift))
- | ((cfg & 0xff) << shift);
+ new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift);
write_csr(pmpcfg0, new);
break;
case 1:
old = read_csr(pmpcfg2);
- new = (old & ~((uintptr_t)0xff << shift))
- | ((cfg & 0xff) << shift);
+ new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift);
write_csr(pmpcfg2, new);
break;
}
@@ -207,8 +201,7 @@
}
/* Generate a PMP configuration of type NA4/NAPOT */
-static pmpcfg_t generate_pmp_napot(
- uintptr_t base, uintptr_t size, uintptr_t flags)
+static pmpcfg_t generate_pmp_napot(uintptr_t base, uintptr_t size, uintptr_t flags)
{
pmpcfg_t p;
flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L);
@@ -219,8 +212,7 @@
}
/* Generate a PMP configuration of type TOR */
-static pmpcfg_t generate_pmp_range(
- uintptr_t base, uintptr_t size, uintptr_t flags)
+static pmpcfg_t generate_pmp_range(uintptr_t base, uintptr_t size, uintptr_t flags)
{
pmpcfg_t p;
flags = flags & (PMP_R | PMP_W | PMP_X | PMP_L);
@@ -280,7 +272,7 @@
for (int i = 0; i < pmp_entries_num(); i++) {
if (read_pmpcfg(i) & PMP_L)
die("Some PMP configurations are locked "
- "and cannot be reset!");
+ "and cannot be reset!");
write_pmpcfg(i, 0);
write_pmpaddr(i, 0);
}
diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
index 0a93763..5ac7023 100644
--- a/src/arch/riscv/smp.c
+++ b/src/arch/riscv/smp.c
@@ -28,7 +28,7 @@
do {
barrier();
- __asm__ volatile ("wfi");
+ __asm__ volatile("wfi");
} while ((read_csr(mip) & MIP_MSIP) == 0);
set_msip(hartid, 0);
HLS()->entry.fn(HLS()->entry.arg);
diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c
index 9fc75f4..e829071 100644
--- a/src/arch/riscv/tables.c
+++ b/src/arch/riscv/tables.c
@@ -12,8 +12,7 @@
void bootmem_arch_add_ranges(void)
{
if (CONFIG(RISCV_OPENSBI) && REGION_SIZE(opensbi) > 0)
- bootmem_add_range((uintptr_t)_opensbi, REGION_SIZE(opensbi),
- BM_MEM_OPENSBI);
+ bootmem_add_range((uintptr_t)_opensbi, REGION_SIZE(opensbi), BM_MEM_OPENSBI);
}
void lb_arch_add_records(struct lb_header *header)
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index fbc6ae4..56a48de 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -33,10 +33,14 @@
static const char *mstatus_to_previous_mode(uintptr_t ms)
{
switch (ms & MSTATUS_MPP) {
- case 0x00000000: return "user";
- case 0x00000800: return "supervisor";
- case 0x00001000: return "hypervisor";
- case 0x00001800: return "machine";
+ case 0x00000000:
+ return "user";
+ case 0x00000800:
+ return "supervisor";
+ case 0x00001000:
+ return "hypervisor";
+ case 0x00001800:
+ return "machine";
}
return "unknown";
@@ -52,16 +56,13 @@
printk(BIOS_DEBUG, "\n");
if (tf->cause < ARRAY_SIZE(exception_names))
- printk(BIOS_DEBUG, "Exception: %s\n",
- exception_names[tf->cause]);
+ printk(BIOS_DEBUG, "Exception: %s\n", exception_names[tf->cause]);
else
- printk(BIOS_DEBUG, "Trap: Unknown cause %p\n",
- (void *)tf->cause);
+ printk(BIOS_DEBUG, "Trap: Unknown cause %p\n", (void *)tf->cause);
previous_mode = mstatus_to_previous_mode(read_csr(mstatus));
printk(BIOS_DEBUG, "Hart ID: %d\n", hart_id);
- printk(BIOS_DEBUG, "Previous mode: %s%s\n",
- previous_mode, mprv? " (MPRV)":"");
+ printk(BIOS_DEBUG, "Previous mode: %s%s\n", previous_mode, mprv ? " (MPRV)" : "");
printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc);
printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr);
printk(BIOS_DEBUG, "Stored ra: %p\n", (void *)tf->gpr[1]);
@@ -101,8 +102,7 @@
break;
default:
printk(BIOS_EMERG, "======================================\n");
- printk(BIOS_EMERG, "coreboot: Unknown machine interrupt: 0x%llx\n",
- cause);
+ printk(BIOS_EMERG, "coreboot: Unknown machine interrupt: 0x%llx\n", cause);
printk(BIOS_EMERG, "======================================\n");
print_trap_information(tf);
break;
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 43e3d70..960cdb9 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -13,23 +13,16 @@
* to M-mode). In practice, this variable has been a lifesaver. It is
* still not quite determined which delegation might by unallowed by
* the spec so for now we enumerate and set them all. */
-static int delegate = 0
- | (1 << CAUSE_MISALIGNED_FETCH)
- | (1 << CAUSE_FETCH_ACCESS)
- | (1 << CAUSE_ILLEGAL_INSTRUCTION)
- | (1 << CAUSE_BREAKPOINT)
- | (1 << CAUSE_LOAD_ACCESS)
- | (1 << CAUSE_STORE_ACCESS)
- | (1 << CAUSE_USER_ECALL)
- | (1 << CAUSE_FETCH_PAGE_FAULT)
- | (1 << CAUSE_LOAD_PAGE_FAULT)
- | (1 << CAUSE_STORE_PAGE_FAULT)
- ;
+static int delegate = 0 | (1 << CAUSE_MISALIGNED_FETCH) | (1 << CAUSE_FETCH_ACCESS) |
+ (1 << CAUSE_ILLEGAL_INSTRUCTION) | (1 << CAUSE_BREAKPOINT) |
+ (1 << CAUSE_LOAD_ACCESS) | (1 << CAUSE_STORE_ACCESS) |
+ (1 << CAUSE_USER_ECALL) | (1 << CAUSE_FETCH_PAGE_FAULT) |
+ (1 << CAUSE_LOAD_PAGE_FAULT) | (1 << CAUSE_STORE_PAGE_FAULT);
void mstatus_init(void)
{
// clear any pending timer interrupts.
- clear_csr(mip, MIP_STIP | MIP_SSIP);
+ clear_csr(mip, MIP_STIP | MIP_SSIP);
// enable machine and supervisor timer and
// all other supervisor interrupts.
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