[coreboot-gerrit] New patch to review for coreboot: soc/intel/common: log event when MRC cache is updated

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17231

-gerrit

commit ab0bc90a3af384355a6c978cd5236ebfad4da8ad
Author: Aaron Durbin 
Date:   Fri Nov 4 10:07:14 2016 -0500

soc/intel/common: log event when MRC cache is updated

Log when the MRC cache is attempted to be updated with status
    of success or failure. Just one slot is supported currently
    which is deemed 'normal'. This is because there are more slots
    anticipated in the future.

BUG=chrome-os-partner:59395

Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da
    Signed-off-by: Aaron Durbin 
---
 src/include/elog.h               | 11 +++++++++++
 src/soc/intel/common/mrc_cache.c | 19 +++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/src/include/elog.h b/src/include/elog.h
index 3df9a4c..3d2a563 100644
--- a/src/include/elog.h
+++ b/src/include/elog.h
@@ -142,6 +142,7 @@ struct elog_event_data_me_extended {
 /* CPU Thermal Trip */
 #define ELOG_TYPE_THERM_TRIP              0xa7

+<<<<<<< HEAD
 /* ARM/generic versions of sleep/wake - These came from another firmware
  * apparently, but not all the firmware sources were updated so that the
  * elog namespace was coherent. */
@@ -149,6 +150,16 @@ struct elog_event_data_me_extended {
 #define ELOG_TYPE_WAKE                   0xa8
 #define ELOG_TYPE_FW_WAKE                0xa9

+/* Memory Cache Update */
+#define ELOG_TYPE_MEM_CACHE_UPDATE        0xaa
+#define  ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL    0
+#define  ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0
+#define  ELOG_MEM_CACHE_UPDATE_STATUS_FAIL    1
+struct elog_event_mem_cache_update {
+	u8 slot;
+	u8 status;
+} __attribute__ ((packed));
+
 #if CONFIG_ELOG
 /* Eventlog backing storage must be initialized before calling elog_init(). */
 extern int elog_init(void);
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index c123da9..bef3ba2 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -17,6 +17,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <cbmem.h>
+#include <elog.h>
 #include <fmap.h>
 #include <ip_checksum.h>
 #include <vboot/vboot_common.h>
@@ -281,6 +282,18 @@ static int protect_mrc_cache(const struct mrc_data_region *region)
    return 0;
 }

+static void log_event_cache_update(uint8_t slot, uint8_t status)
+{
+	const int type = ELOG_TYPE_MEM_CACHE_UPDATE;
+	struct elog_event_mem_cache_update event = {
+		.slot = slot,
+		.status = status,
+	};
+
+	if (elog_add_event_raw(type, &event, sizeof(event)) < 0)
+		printk(BIOS_ERR, "Failed to log mem cache update event.\n");
+}
+
 static void update_mrc_cache(void *unused)
 {
    const struct mrc_saved_data *current_boot;
@@ -336,7 +349,13 @@ static void update_mrc_cache(void *unused)
                   current_boot->size + sizeof(*current_boot))) {
    	printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n",
    	       next_slot);
+		log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL,
+			ELOG_MEM_CACHE_UPDATE_STATUS_FAIL);
+	} else {
+		log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL,
+			ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS);
    }
+
    protect_mrc_cache(&region);
 }