Xiang Wang has uploaded this change for review.

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riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths

Change-Id: Iabe390963bcbeb9ec6016faa8312d101431942da
Signed-off-by: Xiang Wang <wxjstz@126.com>
---
M src/arch/riscv/include/mcall.h
1 file changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31976/1

diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index 192d2b4..652d21b 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -20,14 +20,16 @@
 // nice to have.
 #if __riscv_xlen == 64
 #define HLS_SIZE 88
+/* We save 37 registers, currently. */
+#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8)
 #endif
 
 #if __riscv_xlen == 32
 #define HLS_SIZE 52
+/* We save 37 registers, currently. */
+#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 4)
 #endif
 
-/* We save 37 registers, currently. */
-#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8)
 
 #ifndef __ASSEMBLER__
 

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