Felix Singer has uploaded this change for review.

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soc/intel/skylake: Refactor PEG configuration

Change-Id: I6dd88ce752ce8f0255c424d0e5b2d8ef918885a1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
M src/soc/intel/skylake/romstage/romstage.c
1 file changed, 6 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/44368/1

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 7410925..da5ec9e 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -171,10 +171,8 @@
 	 * in FSP
 	 */
 	dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
-	if (!dev || !dev->enabled)
-		m_cfg->Peg0Enable = 0;
-	else if (dev->enabled) {
-		m_cfg->Peg0Enable = dev->enabled;
+	m_cfg->Peg0Enable = dev && dev->enabled;
+	if (m_cfg->Peg0Enable) {
 		m_cfg->Peg0MaxLinkWidth = config->Peg0MaxLinkWidth;
 		/* Use maximum possible link speed */
 		m_cfg->Peg0MaxLinkSpeed = 0;
@@ -186,10 +184,8 @@
 	}
 
 	dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
-	if (!dev || !dev->enabled)
-		m_cfg->Peg1Enable = 0;
-	else if (dev->enabled) {
-		m_cfg->Peg1Enable = dev->enabled;
+	m_cfg->Peg1Enable = dev && dev->enabled;
+	if (m_cfg->Peg1Enable) {
 		m_cfg->Peg1MaxLinkWidth = config->Peg1MaxLinkWidth;
 		m_cfg->Peg1MaxLinkSpeed = 0;
 		m_cfg->Peg1PowerDownUnusedLanes = 1;
@@ -198,10 +194,8 @@
 	}
 
 	dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
-	if (!dev || !dev->enabled)
-		m_cfg->Peg2Enable = 0;
-	else if (dev->enabled) {
-		m_cfg->Peg2Enable = dev->enabled;
+	m_cfg->Peg2Enable = dev && dev->enabled;
+	if (m_cfg->Peg2Enable) {
 		m_cfg->Peg2MaxLinkWidth = config->Peg2MaxLinkWidth;
 		m_cfg->Peg2MaxLinkSpeed = 0;
 		m_cfg->Peg2PowerDownUnusedLanes = 1;

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