1 comment:
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #4, Line 54: free running CLK
you mean PcieClkSrcUsage[6]="7" ? because CLK6 is for RP6 already. […]
Actually on RVP, CLK6 is MUXed between Gbe and PCIe x1
hence for x1 port to work, doesn't contain port-clock map for a given board,
the clocks will keep on running anyway, allowing PCIe devices to operate.
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