Kyösti Mälkki has uploaded this change for review.
arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
This was used to enforce 4kiB alignment of _start16bit in
romcc bootblock. Platforms requiring this moved away to
C_ENVIRONMENT_BOOTBLOCK that globally forces the alignment.
Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
M src/arch/x86/Kconfig
M src/arch/x86/failover.ld
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/intel/model_106cx/Kconfig
M src/cpu/intel/socket_LGA775/Kconfig
M src/cpu/intel/socket_mPGA604/Kconfig
M src/cpu/x86/16bit/entry16.inc
7 files changed, 5 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30856/1
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 242a7cf..c2fc914 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -81,13 +81,6 @@
default n
depends on ARCH_X86 && SMP
-# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
-# can boot AP CPUs to enable their shared caches.
-config SIPI_VECTOR_IN_ROM
- bool
- default n
- depends on ARCH_X86
-
# Set the rambase for systems that still need it, only 5 chipsets as of
# Sep 2018. This value was 0x100000, chosen to match the entry point
# of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense
diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
index b32aa29..eabc9f7 100644
--- a/src/arch/x86/failover.ld
+++ b/src/arch/x86/failover.ld
@@ -23,12 +23,11 @@
TARGET(binary)
SECTIONS
{
- /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
- * with Startup IPI message without RAM. Align .rom to next 4 byte
- * boundary anyway, so no pad byte appears between _rom and _start.
+ /* Align .rom to 4 byte boundary so no pad byte appears
+ * between _rom and _start.
*/
.bogus ROMLOC_MIN : {
- . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4);
+ . = ALIGN(4);
ROMLOC = .;
} >rom = 0xff
@@ -49,12 +48,7 @@
* may cause the total size of a section to change when the start
* address gets applied.
*/
- ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
- (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
-
- /* Post-check proper SIPI vector. */
- _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff),
- "Address mismatch on AP_SIPI_VECTOR");
+ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
/DISCARD/ : {
*(.comment)
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index fda572d..5c579a1 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -23,10 +23,6 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
-/* Fixed location, ASSERTED in failover.ld if it changes. */
-.set ap_sipi_vector_in_rom, 0xff
-#endif
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index f365cf1..2a324fb 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -7,7 +7,6 @@
select SMP
select SSE2
select UDELAY_LAPIC
- select SIPI_VECTOR_IN_ROM
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 8b227bd..6c3d837 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -13,7 +13,6 @@
select CPU_INTEL_MODEL_1067X
select MMX
select SSE
- select SIPI_VECTOR_IN_ROM
config DCACHE_RAM_SIZE
hex
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index ca2f7b3..e860ded 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -9,7 +9,6 @@
select MMX
select SSE
select UDELAY_TSC
- select SIPI_VECTOR_IN_ROM
select C_ENVIRONMENT_BOOTBLOCK
# mPGA604 are usually Intel Netburst CPUs which should have SSE2
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 2a9f8c5..f110980 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -29,8 +29,7 @@
#include <arch/rom_segs.h>
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \
- IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM)
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
*/
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