Patrick Rudolph has uploaded this change for review.
drivers/intel/fsp2_0: Fix running on x86_64
The FSP info header was using size_t instead of the native data type used to
compile the binary. This caused the FSP-M to not being recognized by the
loader.
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/upd.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/notify.c
M src/drivers/intel/fsp2_0/silicon_init.c
6 files changed, 92 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/48174/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 03b9c2b..4e88795 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -1,5 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only
+config PLATFORM_USES_FSP2_X86_32
+ bool
+ default y
+ help
+ The FSP 2.0 build runs in x86_32 protected mode.
+
+config PLATFORM_USES_FSP2_X86_64
+ bool
+ depends on !PLATFORM_USES_FSP2_X86_32
+ default y
+ help
+ The FSP 2.0 build runs in x86_64 long mode.
+
config PLATFORM_USES_FSP2_0
bool
default n
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
index f237a37..7f09cc6 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -4,6 +4,7 @@
#define _FSP2_0_INFO_HEADER_H_
#include <types.h>
+#include <commonlib/bsd/compiler.h>
#define FSP_HDR_OFFSET 0x94
#if CONFIG(PLATFORM_USES_FSP2_2)
@@ -16,24 +17,46 @@
#define FSP_HDR_ATTRIB_FSPM 2
#define FSP_HDR_ATTRIB_FSPS 3
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
struct fsp_header {
uint32_t fsp_revision;
- size_t image_size;
- uintptr_t image_base;
+ uint32_t image_size;
+ uint32_t image_base;
uint16_t image_attribute;
uint8_t spec_version;
uint16_t component_attribute;
- size_t cfg_region_offset;
- size_t cfg_region_size;
- size_t temp_ram_init_entry;
- size_t temp_ram_exit_entry;
- size_t notify_phase_entry_offset;
- size_t memory_init_entry_offset;
- size_t silicon_init_entry_offset;
- size_t multi_phase_si_init_entry_offset;
+ uint32_t cfg_region_offset;
+ uint32_t cfg_region_size;
+ uint32_t temp_ram_init_entry;
+ uint32_t temp_ram_exit_entry;
+ uint32_t notify_phase_entry_offset;
+ uint32_t memory_init_entry_offset;
+ uint32_t silicon_init_entry_offset;
+ uint32_t multi_phase_si_init_entry_offset;
char image_id[sizeof(uint64_t) + 1];
uint8_t revision;
-};
+} __packed;
+#else
+struct fsp_header {
+ uint32_t fsp_revision;
+ uint64_t image_size;
+ uint64_t image_base;
+ uint16_t image_attribute;
+ uint8_t spec_version;
+ uint16_t component_attribute;
+ uint64_t cfg_region_offset;
+ uint64_t cfg_region_size;
+ uint64_t temp_ram_init_entry;
+ uint64_t temp_ram_exit_entry;
+ uint64_t notify_phase_entry_offset;
+ uint64_t memory_init_entry_offset;
+ uint64_t silicon_init_entry_offset;
+ uint64_t multi_phase_si_init_entry_offset;
+ char image_id[sizeof(uint64_t) + 1];
+ uint8_t revision;
+} __packed;
+#endif
+
enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
index 979cff3..370fcd3 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/upd.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -21,6 +21,7 @@
uint8_t Reserved[23];
} __packed;
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
struct FSPM_ARCH_UPD {
///
/// Revision of the structure. For FSP v2.0 value is 1.
@@ -31,12 +32,12 @@
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
///
- void *NvsBufferPtr;
+ uint32_t NvsBufferPtr;
///
/// Pointer to the temporary stack base address to be
/// consumed inside FspMemoryInit() API.
///
- void *StackBase;
+ uint32_t StackBase;
///
/// Temporary stack size to be consumed inside
/// FspMemoryInit() API.
@@ -53,7 +54,40 @@
uint32_t BootMode;
uint8_t Reserved1[8];
} __packed;
-
+#else
+struct FSPM_ARCH_UPD {
+ ///
+ /// Revision of the structure. For FSP v2.0 value is 1.
+ ///
+ uint8_t Revision;
+ uint8_t Reserved[3];
+ ///
+ /// Pointer to the non-volatile storage (NVS) data buffer.
+ /// If it is NULL it indicates the NVS data is not available.
+ ///
+ uint64_t NvsBufferPtr;
+ ///
+ /// Pointer to the temporary stack base address to be
+ /// consumed inside FspMemoryInit() API.
+ ///
+ uint64_t StackBase;
+ ///
+ /// Temporary stack size to be consumed inside
+ /// FspMemoryInit() API.
+ ///
+ uint32_t StackSize;
+ ///
+ /// Size of memory to be reserved by FSP below "top
+ /// of low usable memory" for bootloader usage.
+ ///
+ uint32_t BootLoaderTolumSize;
+ ///
+ /// Current boot mode.
+ ///
+ uint32_t BootMode;
+ uint8_t Reserved1[8];
+} __packed;
+#endif
struct FSPS_ARCH_UPD {
///
/// Revision of the structure. For FSP v2.2 value is 1.
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 27e34fe..d62888e 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -101,7 +101,7 @@
return;
/* MRC cache found */
- arch_upd->NvsBufferPtr = data;
+ arch_upd->NvsBufferPtr = (uintptr_t)data;
printk(BIOS_SPEW, "MRC cache found, size %zx\n", mrc_size);
}
@@ -142,7 +142,7 @@
stack_end) != CB_SUCCESS)
return CB_ERR;
- arch_upd->StackBase = (void *)stack_begin;
+ arch_upd->StackBase = stack_begin;
return CB_SUCCESS;
}
@@ -237,7 +237,7 @@
fsp_version = fsp_memory_settings_version(hdr);
- upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
+ upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
die_with_post_code(POST_INVALID_VENDOR_BINARY,
@@ -291,7 +291,7 @@
post_code(POST_MEM_PREINIT_PREP_END);
/* Call FspMemoryInit */
- fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
+ fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->memory_init_entry_offset);
fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);
post_code(POST_FSP_MEMORY_INIT);
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index ee04630..73de605 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -15,7 +15,7 @@
if (!fsps_hdr.notify_phase_entry_offset)
die("Notify_phase_entry_offset is zero!\n");
- fspnotify = (void *) (fsps_hdr.image_base +
+ fspnotify = (void *) (uintptr_t)(fsps_hdr.image_base +
fsps_hdr.notify_phase_entry_offset);
fsp_before_debug_notify(fspnotify, ¬ify_params);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 0b6540e..d180060 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -85,7 +85,7 @@
struct fsp_multi_phase_params multi_phase_params;
struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
- supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
+ supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE)
die_with_post_code(POST_INVALID_VENDOR_BINARY,
@@ -111,7 +111,7 @@
logo_entry = soc_load_logo(upd);
/* Call SiliconInit */
- silicon_init = (void *) (hdr->image_base +
+ silicon_init = (void *) (uintptr_t)(hdr->image_base +
hdr->silicon_init_entry_offset);
fsp_debug_before_silicon_init(silicon_init, supd, upd);
@@ -139,7 +139,7 @@
return;
/* Call MultiPhaseSiInit */
- multi_phase_si_init = (void *) (hdr->image_base +
+ multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base +
hdr->multi_phase_si_init_entry_offset);
/* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */
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