[coreboot-gerrit] Change in coreboot[master]: src/intel/xeon_sp: add hardware error support (HEST)

[Arthur Heymans (Code Review)]

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Morgan Jang, Patrick Rudolph, Tim Chu.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52090 )

Change subject: src/intel/xeon_sp: add hardware error support (HEST)
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Patch Set 18: Code-Review-1

(3 comments)

Patchset:

PS18: 
I don't get the gnvs variable.

File src/soc/intel/common/block/acpi/acpi/globalnvs.asl:

https://review.coreboot.org/c/coreboot/+/52090/comment/4d115fc3_0c8dcb9c 
PS18, Line 27: ,	8, 	// 0x40 - 0x48 Hest log buffer
Why is it in gnvs if it's not a variable here?

File src/soc/intel/xeon_sp/uncore.c:

https://review.coreboot.org/c/coreboot/+/52090/comment/201771ae_013d69f1 
PS18, Line 209: cbmem_top()
cbmem_top_addr?