wang qii has uploaded this change for review.
mediatek: Refactor I2C code among similar SOCs
Refactor I2C code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot
Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c
Signed-off-by: qii wang <qii.wang@mediatek.com>
---
A src/soc/mediatek/common/i2c.c
A src/soc/mediatek/common/include/soc/i2c_common.h
M src/soc/mediatek/mt8173/Makefile.inc
M src/soc/mediatek/mt8173/i2c.c
M src/soc/mediatek/mt8173/include/soc/i2c.h
5 files changed, 390 insertions(+), 354 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30975/1
diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c
new file mode 100644
index 0000000..73414ac
--- /dev/null
+++ b/src/soc/mediatek/common/i2c.c
@@ -0,0 +1,273 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <delay.h>
+#include <timer.h>
+#include <symbols.h>
+#include <arch/io.h>
+#include <soc/i2c.h>
+#include <device/i2c_simple.h>
+
+static inline void i2c_dma_reset(struct mt_i2c_dma_regs *dma_regs)
+{
+ write32(&dma_regs->dma_rst, 0x1);
+ udelay(50);
+ write32(&dma_regs->dma_rst, 0x2);
+ udelay(50);
+ write32(&dma_regs->dma_rst, 0x0);
+ udelay(50);
+}
+
+static inline void mtk_i2c_dump_info(uint8_t bus)
+{
+ struct mt_i2c_regs *regs;
+
+ regs = mtk_i2c_bus_controller[bus].i2c_regs;
+
+ printk(BIOS_ERR, "I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\n"
+ "INTR_STAT %x\nCONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\n"
+ "DELAY_LEN %x\nTIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\n"
+ "HS %x\nDEBUGSTAT %x\nEXT_CONF %x\n",
+ (read32(®s->slave_addr)),
+ (read32(®s->intr_mask)),
+ (read32(®s->intr_stat)),
+ (read32(®s->control)),
+ (read32(®s->transfer_len)),
+ (read32(®s->transac_len)),
+ (read32(®s->delay_len)),
+ (read32(®s->timing)),
+ (read32(®s->start)),
+ (read32(®s->fifo_stat)),
+ (read32(®s->io_config)),
+ (read32(®s->hs)),
+ (read32(®s->debug_stat)),
+ (read32(®s->ext_conf)));
+}
+
+static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg,
+ enum i2c_modes read)
+{
+ uint32_t ret_code = I2C_OK;
+ uint16_t status;
+ uint32_t time_out_val = 0;
+ uint8_t addr;
+ uint32_t write_len = 0;
+ uint32_t read_len = 0;
+ uint8_t *write_buffer = NULL;
+ uint8_t *read_buffer = NULL;
+ struct mt_i2c_regs *regs;
+ struct mt_i2c_dma_regs *dma_regs;
+ struct stopwatch sw;
+
+ regs = mtk_i2c_bus_controller[bus].i2c_regs;
+ dma_regs = mtk_i2c_bus_controller[bus].i2c_dma_regs;
+
+ addr = seg[0].slave;
+
+ switch (read) {
+ case I2C_WRITE_MODE:
+ assert(seg[0].len > 0 && seg[0].len <= 255);
+ write_len = seg[0].len;
+ write_buffer = seg[0].buf;
+ break;
+
+ case I2C_READ_MODE:
+ assert(seg[0].len > 0 && seg[0].len <= 255);
+ read_len = seg[0].len;
+ read_buffer = seg[0].buf;
+ break;
+
+ /* Must use special write-then-read mode for repeated starts. */
+ case I2C_WRITE_READ_MODE:
+ assert(seg[0].len > 0 && seg[0].len <= 255);
+ assert(seg[1].len > 0 && seg[1].len <= 255);
+ write_len = seg[0].len;
+ read_len = seg[1].len;
+ write_buffer = seg[0].buf;
+ read_buffer = seg[1].buf;
+ break;
+ }
+
+ /* Clear interrupt status */
+ write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR |
+ I2C_HS_NACKERR);
+
+ write32(®s->fifo_addr_clr, 0x1);
+
+ /* Enable interrupt */
+ write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR |
+ I2C_TRANSAC_COMP);
+
+ switch (read) {
+ case I2C_WRITE_MODE:
+ memcpy(_dma_coherent, write_buffer, write_len);
+
+ /* control registers */
+ write32(®s->control, ASYNC_MODE | DMAACK_EN |
+ ACK_ERR_DET_EN | DMA_EN | CLK_EXT |
+ REPEATED_START_FLAG);
+
+ /* Set transfer and transaction len */
+ write32(®s->transac_len, 1);
+ write32(®s->transfer_len, write_len);
+
+ /* set i2c write slave address*/
+ write32(®s->slave_addr, addr << 1);
+
+ /* Prepare buffer data to start transfer */
+ write32(&dma_regs->dma_con, I2C_DMA_CON_TX);
+ write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent);
+ write32(&dma_regs->dma_tx_len, write_len);
+ break;
+
+ case I2C_READ_MODE:
+ /* control registers */
+ write32(®s->control, ASYNC_MODE | DMAACK_EN |
+ ACK_ERR_DET_EN | DMA_EN | CLK_EXT |
+ REPEATED_START_FLAG);
+
+ /* Set transfer and transaction len */
+ write32(®s->transac_len, 1);
+ write32(®s->transfer_len, read_len);
+
+ /* set i2c read slave address*/
+ write32(®s->slave_addr, (addr << 1 | 0x1));
+
+ /* Prepare buffer data to start transfer */
+ write32(&dma_regs->dma_con, I2C_DMA_CON_RX);
+ write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent);
+ write32(&dma_regs->dma_rx_len, read_len);
+ break;
+
+ case I2C_WRITE_READ_MODE:
+ memcpy(_dma_coherent, write_buffer, write_len);
+
+ /* control registers */
+ write32(®s->control, ASYNC_MODE | DMAACK_EN |
+ DIR_CHG | ACK_ERR_DET_EN | DMA_EN |
+ CLK_EXT | REPEATED_START_FLAG);
+
+ /* Set transfer and transaction len */
+ write32(®s->transfer_len, write_len);
+ write32(®s->transfer_aux_len, read_len);
+ write32(®s->transac_len, 2);
+
+ /* set i2c write slave address*/
+ write32(®s->slave_addr, addr << 1);
+
+ /* Prepare buffer data to start transfer */
+ write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG);
+ write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent);
+ write32(&dma_regs->dma_tx_len, write_len);
+ write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent);
+ write32(&dma_regs->dma_rx_len, read_len);
+ break;
+ }
+
+ write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG);
+ write32(&dma_regs->dma_en, I2C_DMA_START_EN);
+
+ /* start transfer transaction */
+ write32(®s->start, 0x1);
+
+ stopwatch_init_msecs_expire(&sw, 100);
+
+ /* polling mode : see if transaction complete */
+ while (1) {
+ status = read32(®s->intr_stat);
+ if (status & I2C_HS_NACKERR) {
+ ret_code = I2C_TRANSFER_FAIL_HS_NACKERR;
+ printk(BIOS_ERR, "[i2c%d] transfer NACK error\n", bus);
+ mtk_i2c_dump_info(bus);
+ break;
+ } else if (status & I2C_ACKERR) {
+ ret_code = I2C_TRANSFER_FAIL_ACKERR;
+ printk(BIOS_ERR, "[i2c%d] transfer ACK error\n", bus);
+ mtk_i2c_dump_info(bus);
+ break;
+ } else if (status & I2C_TRANSAC_COMP) {
+ ret_code = I2C_OK;
+ memcpy(read_buffer, _dma_coherent, read_len);
+ break;
+ }
+
+ if (stopwatch_expired(&sw)) {
+ ret_code = I2C_TRANSFER_FAIL_TIMEOUT;
+ printk(BIOS_ERR, "[i2c%d] transfer timeout:%d\n", bus,
+ time_out_val);
+ mtk_i2c_dump_info(bus);
+ break;
+ }
+ }
+
+ write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR |
+ I2C_HS_NACKERR);
+
+ /* clear bit mask */
+ write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR |
+ I2C_TRANSAC_COMP);
+
+ /* reset the i2c controller for next i2c transfer. */
+ write32(®s->softreset, 0x1);
+
+ i2c_dma_reset(dma_regs);
+
+ return ret_code;
+}
+
+static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count)
+{
+ if (left_count >= 2 &&
+ !(seg[0].flags & I2C_M_RD) &&
+ (seg[1].flags & I2C_M_RD) &&
+ seg[0].slave == seg[1].slave)
+ return 1;
+ else
+ return 0;
+}
+
+int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments,
+ int seg_count)
+{
+ int ret = 0;
+ int i;
+ int read;
+
+ for (i = 0; i < seg_count; i++) {
+ if (mtk_i2c_should_combine(&segments[i], seg_count - i)) {
+ read = I2C_WRITE_READ_MODE;
+ } else {
+ read = (segments[i].flags & I2C_M_RD) ?
+ I2C_READ_MODE : I2C_WRITE_MODE;
+ }
+
+ ret = mtk_i2c_transfer(bus, &segments[i], read);
+
+ if (ret)
+ break;
+
+ if (read == I2C_WRITE_READ_MODE)
+ i++;
+ }
+
+ return ret;
+}
+
+void mtk_i2c_bus_init(uint8_t bus)
+{
+ mtk_i2c_init(bus);
+}
diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h
new file mode 100755
index 0000000..e455f35
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/i2c_common.h
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MTK_COMMON_I2C_H
+#define MTK_COMMON_I2C_H
+
+/* I2C DMA Registers */
+struct mt_i2c_dma_regs {
+ uint32_t dma_int_flag;
+ uint32_t dma_int_en;
+ uint32_t dma_en;
+ uint32_t dma_rst;
+ uint32_t reserved1;
+ uint32_t dma_flush;
+ uint32_t dma_con;
+ uint32_t dma_tx_mem_addr;
+ uint32_t dma_rx_mem_addr;
+ uint32_t dma_tx_len;
+ uint32_t dma_rx_len;
+};
+
+check_member(mt_i2c_dma_regs, dma_tx_len, 0x24);
+
+/* I2C Configuration */
+enum {
+ I2C_HS_DEFAULT_VALUE = 0x0102,
+};
+
+enum i2c_modes {
+ I2C_WRITE_MODE = 0,
+ I2C_READ_MODE = 1,
+ I2C_WRITE_READ_MODE = 2,
+};
+
+enum {
+ I2C_DMA_CON_TX = 0x0,
+ I2C_DMA_CON_RX = 0x1,
+ I2C_DMA_START_EN = 0x1,
+ I2C_DMA_INT_FLAG_NONE = 0x0,
+ I2C_DMA_CLR_FLAG = 0x0,
+ I2C_DMA_FLUSH_FLAG = 0x1,
+};
+
+enum {
+ I2C_TRANS_LEN_MASK = (0xff),
+ I2C_TRANS_AUX_LEN_MASK = (0x1f << 8),
+ I2C_CONTROL_MASK = (0x3f << 1)
+};
+
+/* Register mask */
+enum {
+ I2C_HS_NACKERR = (1 << 2),
+ I2C_ACKERR = (1 << 1),
+ I2C_TRANSAC_COMP = (1 << 0),
+};
+
+/* i2c control bits */
+enum {
+ ASYNC_MODE = (1 << 9),
+ DMAACK_EN = (1 << 8),
+ ACK_ERR_DET_EN = (1 << 5),
+ DIR_CHG = (1 << 4),
+ CLK_EXT = (1 << 3),
+ DMA_EN = (1 << 2),
+ REPEATED_START_FLAG = (1 << 1),
+ STOP_FLAG = (0 << 1)
+};
+
+/* I2C Status Code */
+
+enum {
+ I2C_OK = 0x0000,
+ I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001,
+ I2C_TRANSFER_INVALID_LENGTH = 0xA002,
+ I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003,
+ I2C_TRANSFER_FAIL_ACKERR = 0xA004,
+ I2C_TRANSFER_FAIL_TIMEOUT = 0xA005,
+ I2C_TRANSFER_INVALID_ARGUMENT = 0xA006
+};
+
+struct mtk_i2c {
+ struct mt_i2c_regs *i2c_regs;
+ struct mt_i2c_dma_regs *i2c_dma_regs;
+};
+
+extern struct mtk_i2c mtk_i2c_bus_controller[];
+
+void mtk_i2c_bus_init(uint8_t bus);
+#endif
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index b004c27..5a54d6d 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -17,7 +17,7 @@
bootblock-y += bootblock.c
bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
-bootblock-y += i2c.c
+bootblock-y += ../common/i2c.c i2c.c
bootblock-y += ../common/pll.c pll.c
bootblock-y += ../common/spi.c spi.c
bootblock-y += ../common/timer.c
@@ -32,7 +32,7 @@
################################################################################
-verstage-y += i2c.c
+verstage-y += ../common/i2c.c i2c.c
verstage-y += ../common/spi.c spi.c
verstage-y += ../common/uart.c
@@ -49,7 +49,7 @@
romstage-y += ../common/pll.c pll.c
romstage-y += ../common/timer.c
romstage-y += timer.c
-romstage-y += i2c.c
+romstage-y += ../common/i2c.c i2c.c
romstage-y += ../common/uart.c
romstage-y += ../common/cbmem.c
@@ -71,7 +71,8 @@
ramstage-y += ../common/timer.c
ramstage-y += timer.c
ramstage-y += ../common/uart.c
-ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c
+ramstage-y += ../common/i2c.c i2c.c
+ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c
ramstage-y += mt6311.c
ramstage-y += da9212.c
ramstage-y += ../common/gpio.c gpio.c
diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c
index b4c3aa9..85f676c 100644
--- a/src/soc/mediatek/mt8173/i2c.c
+++ b/src/soc/mediatek/mt8173/i2c.c
@@ -14,19 +14,13 @@
*/
#include <assert.h>
-#include <delay.h>
-#include <device/i2c_simple.h>
-#include <string.h>
-#include <symbols.h>
-#include <timer.h>
#include <arch/io.h>
-#include <soc/addressmap.h>
-#include <soc/i2c.h>
#include <soc/pll.h>
+#include <soc/i2c.h>
#define I2C_CLK_HZ (AXI_HZ / 16)
-static struct mtk_i2c i2c[7] = {
+struct mtk_i2c mtk_i2c_bus_controller[7] = {
/* i2c0 setting */
{
.i2c_regs = (void *)I2C_BASE,
@@ -68,277 +62,21 @@
}
};
-#define I2CTAG "[I2C][PL] "
-
-#if IS_ENABLED(CONFIG_DEBUG_I2C)
-#define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg)
-#else
-#define I2CLOG(fmt, arg...)
-#endif /* CONFIG_DEBUG_I2C */
-
-#define I2CERR(fmt, arg...) printk(BIOS_ERR, I2CTAG fmt, ##arg)
-
-static inline void i2c_dma_reset(struct mt8173_i2c_dma_regs *dma_regs)
+void mtk_i2c_init(uint8_t bus)
{
- write32(&dma_regs->dma_rst, 0x1);
- udelay(50);
- write32(&dma_regs->dma_rst, 0x2);
- udelay(50);
- write32(&dma_regs->dma_rst, 0x0);
- udelay(50);
-}
-
-void mtk_i2c_bus_init(uint8_t bus)
-{
- uint8_t sample_div;
uint8_t step_div;
uint32_t i2c_freq;
+ const uint8_t sample_div = 1;
- assert(bus < ARRAY_SIZE(i2c));
+ assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller));
/* Calculate i2c frequency */
- sample_div = 1;
step_div = DIV_ROUND_UP(I2C_CLK_HZ, (400 * KHz * sample_div * 2));
i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2);
assert(sample_div < 8 && step_div < 64 && i2c_freq < 400 * KHz &&
i2c_freq >= 380 * KHz);
/* Init i2c bus Timing register */
- write32(&i2c[bus].i2c_regs->timing, (sample_div - 1) << 8 |
- (step_div - 1));
-}
-
-static inline void mtk_i2c_dump_info(uint8_t bus)
-{
- struct mt8173_i2c_regs *regs;
-
- regs = i2c[bus].i2c_regs;
-
- I2CLOG("I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\nINTR_STAT %x\n"
- "CONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\nDELAY_LEN %x\n"
- "TIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\nHS %x\n"
- "DEBUGSTAT %x\nEXT_CONF %x\n",
- (read32(®s->salve_addr)),
- (read32(®s->intr_mask)),
- (read32(®s->intr_stat)),
- (read32(®s->control)),
- (read32(®s->transfer_len)),
- (read32(®s->transac_len)),
- (read32(®s->delay_len)),
- (read32(®s->timing)),
- (read32(®s->start)),
- (read32(®s->fifo_stat)),
- (read32(®s->io_config)),
- (read32(®s->hs)),
- (read32(®s->debug_stat)),
- (read32(®s->ext_conf)));
-
- I2CLOG("addr address %x\n", (uint32_t)regs);
-}
-
-static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg,
- enum i2c_modes read)
-{
- uint32_t ret_code = I2C_OK;
- uint16_t status;
- uint32_t time_out_val = 0;
- uint8_t addr;
- uint32_t write_len = 0;
- uint32_t read_len = 0;
- uint8_t *write_buffer = NULL;
- uint8_t *read_buffer = NULL;
- struct mt8173_i2c_regs *regs;
- struct mt8173_i2c_dma_regs *dma_regs;
- struct stopwatch sw;
-
- regs = i2c[bus].i2c_regs;
- dma_regs = i2c[bus].i2c_dma_regs;
-
- addr = seg[0].slave;
-
- switch (read) {
- case I2C_WRITE_MODE:
- assert(seg[0].len > 0 && seg[0].len <= 255);
- write_len = seg[0].len;
- write_buffer = seg[0].buf;
- break;
-
- case I2C_READ_MODE:
- assert(seg[0].len > 0 && seg[0].len <= 255);
- read_len = seg[0].len;
- read_buffer = seg[0].buf;
- break;
-
- /* Must use special write-then-read mode for repeated starts. */
- case I2C_WRITE_READ_MODE:
- assert(seg[0].len > 0 && seg[0].len <= 255);
- assert(seg[1].len > 0 && seg[1].len <= 255);
- write_len = seg[0].len;
- read_len = seg[1].len;
- write_buffer = seg[0].buf;
- read_buffer = seg[1].buf;
- break;
- }
-
- /* Clear interrupt status */
- write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR |
- I2C_HS_NACKERR);
-
- write32(®s->fifo_addr_clr, 0x1);
-
- /* Enable interrupt */
- write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR |
- I2C_TRANSAC_COMP);
-
- switch (read) {
- case I2C_WRITE_MODE:
- memcpy(_dma_coherent, write_buffer, write_len);
-
- /* control registers */
- write32(®s->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT |
- REPEATED_START_FLAG);
-
- /* Set transfer and transaction len */
- write32(®s->transac_len, 1);
- write32(®s->transfer_len, write_len);
-
- /* set i2c write slave address*/
- write32(®s->slave_addr, addr << 1);
-
- /* Prepare buffer data to start transfer */
- write32(&dma_regs->dma_con, I2C_DMA_CON_TX);
- write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent);
- write32(&dma_regs->dma_tx_len, write_len);
- break;
-
- case I2C_READ_MODE:
- /* control registers */
- write32(®s->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT |
- REPEATED_START_FLAG);
-
- /* Set transfer and transaction len */
- write32(®s->transac_len, 1);
- write32(®s->transfer_len, read_len);
-
- /* set i2c read slave address*/
- write32(®s->slave_addr, (addr << 1 | 0x1));
-
- /* Prepare buffer data to start transfer */
- write32(&dma_regs->dma_con, I2C_DMA_CON_RX);
- write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent);
- write32(&dma_regs->dma_rx_len, read_len);
- break;
-
- case I2C_WRITE_READ_MODE:
- memcpy(_dma_coherent, write_buffer, write_len);
-
- /* control registers */
- write32(®s->control, DIR_CHG | ACK_ERR_DET_EN | DMA_EN |
- CLK_EXT | REPEATED_START_FLAG);
-
- /* Set transfer and transaction len */
- write32(®s->transfer_len, write_len);
- write32(®s->transfer_aux_len, read_len);
- write32(®s->transac_len, 2);
-
- /* set i2c write slave address*/
- write32(®s->slave_addr, addr << 1);
-
- /* Prepare buffer data to start transfer */
- write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG);
- write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent);
- write32(&dma_regs->dma_tx_len, write_len);
- write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent);
- write32(&dma_regs->dma_rx_len, read_len);
- break;
- }
-
- write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG);
- write32(&dma_regs->dma_en, I2C_DMA_START_EN);
-
- /* start transfer transaction */
- write32(®s->start, 0x1);
-
- stopwatch_init_msecs_expire(&sw, 100);
-
- /* polling mode : see if transaction complete */
- while (1) {
- status = read32(®s->intr_stat);
- if (status & I2C_HS_NACKERR) {
- ret_code = I2C_TRANSFER_FAIL_HS_NACKERR;
- I2CERR("[i2c%d transfer] transaction NACK error\n",
- bus);
- mtk_i2c_dump_info(bus);
- break;
- } else if (status & I2C_ACKERR) {
- ret_code = I2C_TRANSFER_FAIL_ACKERR;
- I2CERR("[i2c%d transfer] transaction ACK error\n", bus);
- mtk_i2c_dump_info(bus);
- break;
- } else if (status & I2C_TRANSAC_COMP) {
- ret_code = I2C_OK;
- memcpy(read_buffer, _dma_coherent, read_len);
- break;
- }
-
- if (stopwatch_expired(&sw)) {
- ret_code = I2C_TRANSFER_FAIL_TIMEOUT;
- I2CERR("[i2c%d transfer] transaction timeout:%d\n", bus,
- time_out_val);
- mtk_i2c_dump_info(bus);
- break;
- }
- }
-
- write32(®s->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR |
- I2C_HS_NACKERR);
-
- /* clear bit mask */
- write32(®s->intr_mask, I2C_HS_NACKERR | I2C_ACKERR |
- I2C_TRANSAC_COMP);
-
- /* reset the i2c controller for next i2c transfer. */
- write32(®s->softreset, 0x1);
-
- i2c_dma_reset(dma_regs);
-
- return ret_code;
-}
-
-static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count)
-{
- if (left_count >= 2 &&
- !(seg[0].flags & I2C_M_RD) &&
- (seg[1].flags & I2C_M_RD) &&
- seg[0].slave == seg[1].slave)
- return 1;
- else
- return 0;
-}
-
-int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
- int seg_count)
-{
- int ret = 0;
- int i;
- int read;
-
- for (i = 0; i < seg_count; i++) {
- if (mtk_i2c_should_combine(&segments[i], seg_count - i)) {
- read = I2C_WRITE_READ_MODE;
- } else {
- read = (segments[i].flags & I2C_M_RD) ?
- I2C_READ_MODE : I2C_WRITE_MODE;
- }
-
- ret = mtk_i2c_transfer(bus, &segments[i], read);
-
- if (ret)
- break;
-
- if (read == I2C_WRITE_READ_MODE)
- i++;
- }
-
- return ret;
+ write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing,
+ (sample_div - 1) << 8 | (step_div - 1));
}
diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h
old mode 100644
new mode 100755
index 5f46e9c..f2f9cf2
--- a/src/soc/mediatek/mt8173/include/soc/i2c.h
+++ b/src/soc/mediatek/mt8173/include/soc/i2c.h
@@ -16,47 +16,10 @@
#ifndef SOC_MEDIATEK_MT8173_I2C_H
#define SOC_MEDIATEK_MT8173_I2C_H
-#include <stddef.h>
-
-/* I2C Configuration */
-enum {
- I2C_HS_DEFAULT_VALUE = 0x0102,
-};
-
-enum i2c_modes {
- I2C_WRITE_MODE = 0,
- I2C_READ_MODE = 1,
- I2C_WRITE_READ_MODE = 2,
-};
-
-enum {
- I2C_DMA_CON_TX = 0x0,
- I2C_DMA_CON_RX = 0x1,
- I2C_DMA_START_EN = 0x1,
- I2C_DMA_INT_FLAG_NONE = 0x0,
- I2C_DMA_CLR_FLAG = 0x0,
- I2C_DMA_FLUSH_FLAG = 0x1,
-};
-
-/* I2C DMA Registers */
-struct mt8173_i2c_dma_regs {
- uint32_t dma_int_flag;
- uint32_t dma_int_en;
- uint32_t dma_en;
- uint32_t dma_rst;
- uint32_t reserved1;
- uint32_t dma_flush;
- uint32_t dma_con;
- uint32_t dma_tx_mem_addr;
- uint32_t dma_rx_mem_addr;
- uint32_t dma_tx_len;
- uint32_t dma_rx_len;
-};
-
-check_member(mt8173_i2c_dma_regs, dma_tx_len, 0x24);
+#include <soc/i2c_common.h>
/* I2C Register */
-struct mt8173_i2c_regs {
+struct mt_i2c_regs {
uint32_t data_port;
uint32_t slave_addr;
uint32_t intr_mask;
@@ -85,48 +48,8 @@
uint32_t transfer_aux_len;
};
-check_member(mt8173_i2c_regs, debug_stat, 0x64);
+check_member(mt_i2c_regs, debug_stat, 0x64);
-struct mtk_i2c {
- struct mt8173_i2c_regs *i2c_regs;
- struct mt8173_i2c_dma_regs *i2c_dma_regs;
-};
-
-enum {
- I2C_TRANS_LEN_MASK = (0xff),
- I2C_TRANS_AUX_LEN_MASK = (0x1f << 8),
- I2C_CONTROL_MASK = (0x3f << 1)
-};
-
-/* Register mask */
-enum {
- I2C_HS_NACKERR = (1 << 2),
- I2C_ACKERR = (1 << 1),
- I2C_TRANSAC_COMP = (1 << 0),
-};
-
-/* i2c control bits */
-enum {
- ACK_ERR_DET_EN = (1 << 5),
- DIR_CHG = (1 << 4),
- CLK_EXT = (1 << 3),
- DMA_EN = (1 << 2),
- REPEATED_START_FLAG = (1 << 1),
- STOP_FLAG = (0 << 1)
-};
-
-/* I2C Status Code */
-
-enum {
- I2C_OK = 0x0000,
- I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001,
- I2C_TRANSFER_INVALID_LENGTH = 0xA002,
- I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003,
- I2C_TRANSFER_FAIL_ACKERR = 0xA004,
- I2C_TRANSFER_FAIL_TIMEOUT = 0xA005,
- I2C_TRANSFER_INVALID_ARGUMENT = 0xA006
-};
-
-void mtk_i2c_bus_init(uint8_t bus);
+void mtk_i2c_init(uint8_t bus);
#endif /* SOC_MEDIATEK_MT8173_I2C_H */
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