Tim Wawrzynczak has uploaded this change for review.
mb/google/brya: Clear SLP_S0_GATE_L on S5 shutdown
On brya platforms, the SLP_S0_L signal is gated to the rest of the
platform by SLP_S0_GATE_L, which is under software control. Currently,
this GPIO is not touched on the powerdown sequence, leading to the
rest of the platform observing the SLP_S0_L signal deassert far too
late, and thus the EC gets confused.
Currently, the EC power state machine observes the following
transitions during powerdown:
S0->S3->S5->G3->S3->S5->G3
With this patch:
S0->S3->S5->G3
BUG=b:186707518
TEST=observe power state transitions in EC console as described above
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5500e701ac8731d141b51dc381609c80047dc1f8
---
M src/mainboard/google/brya/mainboard.asl
M src/mainboard/google/brya/wwan_power.asl
2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/58180/1
diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl
index c60db30..330bcc3 100644
--- a/src/mainboard/google/brya/mainboard.asl
+++ b/src/mainboard/google/brya/mainboard.asl
@@ -22,3 +22,18 @@
\_SB.PCI0.STXS(GPIO_SLP_S0_GATE);
}
}
+
+/* Mainboard _PTS override */
+Method (MPTS, 1)
+{
+ /*
+ * On S5 shutdown, clear the SLP_S0_GATE pin, so that the rest of the
+ * platform can observe SLP_S0_L transition at the correct point in
+ * the shutdown sequence.
+ */
+ \_SB.PCI0.CTXS(GPIO_SLP_S0_GATE);
+
+#if CONFIG(HAVE_WWAN_POWER_SEQUENCE)
+ WWPD()
+#endif
+}
diff --git a/src/mainboard/google/brya/wwan_power.asl b/src/mainboard/google/brya/wwan_power.asl
index d9bb5e7..4f33152 100644
--- a/src/mainboard/google/brya/wwan_power.asl
+++ b/src/mainboard/google/brya/wwan_power.asl
@@ -2,7 +2,7 @@
#include <variant/gpio.h>
-Method (MPTS, 1)
+Method (WWPD, 0)
{
\_SB.PCI0.CTXS(WWAN_PERST);
Sleep(T1_OFF_MS)
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