Chen Wisley would like Wisley Chen to review this change.
mb/google/volteer/var/elemi: Disable Pcie setting for non-emmc sku
BUG=none
BRANCH=volteer
TEST=emerge-volteer coreboot
Change-Id: I5fbdb9de81066100d28040bdbc044b8cec10188f
---
M src/mainboard/google/volteer/variants/elemi/Makefile.inc
A src/mainboard/google/volteer/variants/elemi/variant.c
2 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47355/1
diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc
index b0bfc56..e34a40b 100644
--- a/src/mainboard/google/volteer/variants/elemi/Makefile.inc
+++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc
@@ -5,3 +5,4 @@
romstage-y += memory.c
ramstage-y += gpio.c
+ramstage-y += variant.c
diff --git a/src/mainboard/google/volteer/variants/elemi/variant.c b/src/mainboard/google/volteer/variants/elemi/variant.c
new file mode 100644
index 0000000..4e14e1a
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/elemi/variant.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <chip.h>
+#include <soc/pci_devs.h>
+#include <ec/google/chromeec/ec.h>
+#include <fw_config.h>
+
+void variant_devtree_update(void)
+{
+ config_t *cfg = config_of_soc();
+ if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_PRESENT))){
+ if (cfg) {
+ cfg->PcieRpEnable[4] = 0;
+ cfg->PcieRpLtrEnable[4] = 0;
+ cfg->PcieRpHotPlug[4] = 0;
+ cfg->PcieClkSrcUsage[5] = 0xff;
+ cfg->PcieClkSrcClkReq[5] = 0xff;
+ }
+ }
+}
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