Arthur Heymans uploaded patch set #6 to this change.

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soc/intel/braswell: Use common cpu/intel/car code

The code in cpu/intel/car/romstage.c Does most of the things like
setting up timestamps, stack guards, entering postcar.

A functional difference is that the FSP header is searched for twice
instead of passed from the CAR entry to the C code. When using
C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special
linker symbol kept across multiple stages is needed, which is likely
not worth the speedup).

Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/include/fsp/car.h
M src/soc/intel/braswell/romstage/Makefile.inc
4 files changed, 34 insertions(+), 96 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32963/6

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