Attention is currently required from: Julius Werner.
Martin L Roth has uploaded this change for review.
arch/arm: Reformat C files with clang-format v16
Reformat only - No functional changes.
Change-Id: Icace93f70f024f8690172e030d0922973beb2727
Signed-off-by: Martin Roth <gaumless@gmail.com>
---
M src/arch/arm/armv4/cache.c
M src/arch/arm/armv7/cache.c
M src/arch/arm/armv7/cache_m.c
M src/arch/arm/armv7/exception.c
M src/arch/arm/armv7/mmu.c
M src/arch/arm/clock.c
M src/arch/arm/eabi_compat.c
M src/arch/arm/fit_payload.c
M src/arch/arm/tables.c
9 files changed, 99 insertions(+), 110 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/80008/1
diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c
index 0ed11ac..019adc0 100644
--- a/src/arch/arm/armv4/cache.c
+++ b/src/arch/arm/armv4/cache.c
@@ -34,15 +34,15 @@
return 64;
}
-void dcache_clean_by_mva(void const *addr, size_t len)
+void dcache_clean_by_mva(const void *addr, size_t len)
{
}
-void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
+void dcache_clean_invalidate_by_mva(const void *addr, size_t len)
{
}
-void dcache_invalidate_by_mva(void const *addr, size_t len)
+void dcache_invalidate_by_mva(const void *addr, size_t len)
{
}
diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
index 1c46e04..9846a37 100644
--- a/src/arch/arm/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -37,8 +37,8 @@
ccsidr = read_ccsidr();
/* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */
- line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */
- line_bytes *= sizeof(unsigned int); /* bytes per line */
+ line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */
+ line_bytes *= sizeof(unsigned int); /* bytes per line */
return line_bytes;
}
@@ -49,7 +49,7 @@
* perform cache maintenance on a particular memory range rather than the
* entire cache.
*/
-static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op)
+static void dcache_op_mva(const void *addr, size_t len, enum dcache_op op)
{
unsigned long line, linesize;
@@ -76,17 +76,17 @@
isb();
}
-void dcache_clean_by_mva(void const *addr, size_t len)
+void dcache_clean_by_mva(const void *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCCMVAC);
}
-void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
+void dcache_clean_invalidate_by_mva(const void *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCCIMVAC);
}
-void dcache_invalidate_by_mva(void const *addr, size_t len)
+void dcache_invalidate_by_mva(const void *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCIMVAC);
}
@@ -126,7 +126,7 @@
else if (sctlr & SCTLR_I)
dcache_clean_invalidate_all();
- iciallu(); /* includes BPIALLU (architecturally) */
+ iciallu(); /* includes BPIALLU (architecturally) */
dsb();
isb();
}
diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c
index 06ed599..311216c 100644
--- a/src/arch/arm/armv7/cache_m.c
+++ b/src/arch/arm/armv7/cache_m.c
@@ -26,15 +26,15 @@
return 0;
}
-void dcache_clean_by_mva(void const *addr, size_t len)
+void dcache_clean_by_mva(const void *addr, size_t len)
{
}
-void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
+void dcache_clean_invalidate_by_mva(const void *addr, size_t len)
{
}
-void dcache_invalidate_by_mva(void const *addr, size_t len)
+void dcache_invalidate_by_mva(const void *addr, size_t len)
{
}
diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c
index 799ae02..d98686c 100644
--- a/src/arch/arm/armv7/exception.c
+++ b/src/arch/arm/armv7/exception.c
@@ -53,7 +53,7 @@
void exception_undefined_instruction(uint32_t *regs)
{
printk(BIOS_ERR, "exception _undefined_instruction\n");
- regs[15] -= 2; /* CAREFUL: specific to thumb mode (otherwise 4)! */
+ regs[15] -= 2; /* CAREFUL: specific to thumb mode (otherwise 4)! */
print_regs(regs);
dump_stack(regs[13], 512);
die("exception");
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index 66ce533..3cbbd53 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -12,30 +12,29 @@
#if CONFIG(ARM_LPAE)
/* See B3.6.2 of ARMv7 Architecture Reference Manual */
/* TODO: Utilize the contiguous hint flag */
-#define ATTR_BLOCK (\
- 0ULL << 54 | /* XN. 0:Not restricted */ \
- 0ULL << 53 | /* PXN. 0:Not restricted */ \
- 1 << 10 | /* AF. 1:Accessed. This is to prevent access */ \
- /* fault when accessed for the first time */ \
- 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
- 0 << 5 | /* NS. 0:Output address is in Secure space */ \
- 0 << 1 | /* block/table. 0:block entry */ \
- 1 << 0 /* validity. 1:valid */ \
+#define ATTR_BLOCK \
+ (0ULL << 54 | /* XN. 0:Not restricted */ \
+ 0ULL << 53 | /* PXN. 0:Not restricted */ \
+ 1 << 10 | /* AF. 1:Accessed. This is to prevent access fault when accessed for the first time */ \
+ 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \
+ 0 << 5 | /* NS. 0:Output address is in Secure space */ \
+ 0 << 1 | /* block/table. 0:block entry */ \
+ 1 << 0 /* validity. 1:valid */ \
)
-#define ATTR_PAGE (ATTR_BLOCK | 1 << 1)
-#define ATTR_NEXTLEVEL (0x3)
-#define ATTR_NC ((MAIR_INDX_NC << 2) | (1ULL << 53) | (1ULL << 54))
-#define ATTR_WT (MAIR_INDX_WT << 2)
-#define ATTR_WB (MAIR_INDX_WB << 2)
+#define ATTR_PAGE (ATTR_BLOCK | 1 << 1)
+#define ATTR_NEXTLEVEL (0x3)
+#define ATTR_NC ((MAIR_INDX_NC << 2) | (1ULL << 53) | (1ULL << 54))
+#define ATTR_WT (MAIR_INDX_WT << 2)
+#define ATTR_WB (MAIR_INDX_WB << 2)
-#define PAGE_MASK 0x000ffffffffff000ULL
-#define BLOCK_MASK 0x000fffffffe00000ULL
-#define NEXTLEVEL_MASK PAGE_MASK
-#define BLOCK_SHIFT 21
+#define PAGE_MASK 0x000ffffffffff000ULL
+#define BLOCK_MASK 0x000fffffffe00000ULL
+#define NEXTLEVEL_MASK PAGE_MASK
+#define BLOCK_SHIFT 21
typedef uint64_t pte_t;
-#else /* CONFIG_ARM_LPAE */
- /*
+#else /* CONFIG_ARM_LPAE */
+/*
* Section entry bits:
* 31:20 - section base address
* 18 - 0 to indicate normal section (versus supersection)
@@ -51,39 +50,39 @@
* 2 - B, 1 for bufferable
* 1: 0 - 0b10 to indicate section entry
*/
-#define ATTR_BLOCK ((3 << 10) | 0x2)
-#define ATTR_PAGE ((3 << 4) | 0x2)
-#define ATTR_NEXTLEVEL (0x1)
-#define ATTR_NC (1 << 4)
-#define ATTR_WT (1 << 3)
-#define ATTR_WB ((1 << 3) | (1 << 2))
+#define ATTR_BLOCK ((3 << 10) | 0x2)
+#define ATTR_PAGE ((3 << 4) | 0x2)
+#define ATTR_NEXTLEVEL (0x1)
+#define ATTR_NC (1 << 4)
+#define ATTR_WT (1 << 3)
+#define ATTR_WB ((1 << 3) | (1 << 2))
-#define PAGE_MASK 0xfffff000UL
-#define BLOCK_MASK 0xfff00000UL
-#define NEXTLEVEL_MASK 0xfffffc00UL
-#define BLOCK_SHIFT 20
+#define PAGE_MASK 0xfffff000UL
+#define BLOCK_MASK 0xfff00000UL
+#define NEXTLEVEL_MASK 0xfffffc00UL
+#define BLOCK_SHIFT 20
typedef uint32_t pte_t;
-#endif /* CONFIG_ARM_LPAE */
+#endif /* CONFIG_ARM_LPAE */
/* We set the first PTE to a sentinel value that cannot occur naturally (has
* attributes set but bits [1:0] are 0 -> unmapped) to mark unused subtables. */
-#define ATTR_UNUSED 0xBADbA6E0
-#define SUBTABLE_PTES (1 << (BLOCK_SHIFT - PAGE_SHIFT))
+#define ATTR_UNUSED 0xBADbA6E0
+#define SUBTABLE_PTES (1 << (BLOCK_SHIFT - PAGE_SHIFT))
/*
* mask/shift/size for pages and blocks
*/
-#define PAGE_SHIFT 12
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
-#define BLOCK_SIZE (1UL << BLOCK_SHIFT)
+#define PAGE_SHIFT 12
+#define PAGE_SIZE (1UL << PAGE_SHIFT)
+#define BLOCK_SIZE (1UL << BLOCK_SHIFT)
/*
* MAIR Index
*/
-#define MAIR_INDX_NC 0
-#define MAIR_INDX_WT 1
-#define MAIR_INDX_WB 2
+#define MAIR_INDX_NC 0
+#define MAIR_INDX_WT 1
+#define MAIR_INDX_WB 2
static pte_t *const ttb_buff = (void *)_ttb;
@@ -91,16 +90,16 @@
pte_t value;
const char *name;
} attrs[] = {
- [DCACHE_OFF] = {.value = ATTR_NC, .name = "uncached"},
- [DCACHE_WRITEBACK] = {.value = ATTR_WB, .name = "writeback"},
+ [DCACHE_OFF] = {.value = ATTR_NC, .name = "uncached" },
+ [DCACHE_WRITEBACK] = {.value = ATTR_WB, .name = "writeback" },
[DCACHE_WRITETHROUGH] = {.value = ATTR_WT, .name = "writethrough"},
};
/* Fills page table entries in |table| from |start_idx| to |end_idx| with |attr|
* and performs necessary invalidations. |offset| is the start address of the
* area described by |table|, and |shift| is the size-shift of each frame. */
-static void mmu_fill_table(pte_t *table, u32 start_idx, u32 end_idx,
- uintptr_t offset, u32 shift, pte_t attr)
+static void mmu_fill_table(pte_t *table, u32 start_idx, u32 end_idx, uintptr_t offset,
+ u32 shift, pte_t attr)
{
int i;
@@ -133,8 +132,8 @@
/* We assume that *pgd_entry must already be a valid block mapping. */
uintptr_t start_addr = (uintptr_t)(*pgd_entry & BLOCK_MASK);
- printk(BIOS_DEBUG, "Creating new subtable @%p for [%#.8lx:%#.8lx)\n",
- table, start_addr, start_addr + BLOCK_SIZE);
+ printk(BIOS_DEBUG, "Creating new subtable @%p for [%#.8lx:%#.8lx)\n", table, start_addr,
+ start_addr + BLOCK_SIZE);
/* Initialize the new subtable with entries of the same attributes
* (XN bit moves from 4 to 0, set PAGE unless block was unmapped). */
@@ -158,12 +157,13 @@
static pte_t *mmu_validate_create_sub_table(u32 start_kb, u32 size_kb)
{
- pte_t *pgd_entry = &ttb_buff[start_kb / (BLOCK_SIZE/KiB)];
+ pte_t *pgd_entry = &ttb_buff[start_kb / (BLOCK_SIZE / KiB)];
pte_t *table = (void *)(uintptr_t)(*pgd_entry & NEXTLEVEL_MASK);
/* Make sure the range is contained within a single superpage. */
- assert(((start_kb + size_kb - 1) & (BLOCK_MASK/KiB))
- == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB));
+ assert(((start_kb + size_kb - 1) & (BLOCK_MASK / KiB)) ==
+ (start_kb & (BLOCK_MASK / KiB)) &&
+ start_kb < 4 * (GiB / KiB));
if ((*pgd_entry & ~NEXTLEVEL_MASK) != ATTR_NEXTLEVEL)
table = mmu_create_subtable(pgd_entry);
@@ -181,17 +181,15 @@
attr = ((attr & ~(1 << 4)) | (1 << 0));
/* Mask away high address bits that are handled by upper level table. */
- u32 mask = BLOCK_SIZE/KiB - 1;
- printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n",
- start_kb * KiB, (start_kb + size_kb) * KiB, attrs[policy].name);
+ u32 mask = BLOCK_SIZE / KiB - 1;
+ printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n", start_kb * KiB,
+ (start_kb + size_kb) * KiB, attrs[policy].name);
- u32 end_kb = ALIGN_UP((start_kb + size_kb), PAGE_SIZE/KiB) -
- (start_kb & ~mask);
+ u32 end_kb = ALIGN_UP((start_kb + size_kb), PAGE_SIZE / KiB) - (start_kb & ~mask);
- assert(end_kb <= BLOCK_SIZE/KiB);
+ assert(end_kb <= BLOCK_SIZE / KiB);
- mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB),
- end_kb / (PAGE_SIZE/KiB),
+ mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE / KiB), end_kb / (PAGE_SIZE / KiB),
(start_kb & ~mask) * KiB, PAGE_SHIFT, ATTR_PAGE | attr);
}
@@ -200,32 +198,31 @@
pte_t *table = mmu_validate_create_sub_table(start_kb, size_kb);
/* Mask away high address bits that are handled by upper level table. */
- u32 mask = BLOCK_SIZE/KiB - 1;
- printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n",
- start_kb * KiB, (start_kb + size_kb) * KiB);
- mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB),
- DIV_ROUND_UP((start_kb + size_kb) & mask, PAGE_SIZE/KiB),
+ u32 mask = BLOCK_SIZE / KiB - 1;
+ printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n", start_kb * KiB,
+ (start_kb + size_kb) * KiB);
+ mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE / KiB),
+ DIV_ROUND_UP((start_kb + size_kb) & mask, PAGE_SIZE / KiB),
(start_kb & ~mask) * KiB, PAGE_SHIFT, 0);
}
void mmu_disable_range(u32 start_mb, u32 size_mb)
{
- printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n",
- start_mb * MiB, (start_mb + size_mb) * MiB);
- assert(start_mb + size_mb <= 4 * (GiB/MiB));
- mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB),
- DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE/MiB),
- 0, BLOCK_SHIFT, 0);
+ printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n", start_mb * MiB,
+ (start_mb + size_mb) * MiB);
+ assert(start_mb + size_mb <= 4 * (GiB / MiB));
+ mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE / MiB),
+ DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE / MiB), 0, BLOCK_SHIFT, 0);
}
void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy)
{
- printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n",
- start_mb * MiB, (start_mb + size_mb) * MiB, attrs[policy].name);
- assert(start_mb + size_mb <= 4 * (GiB/MiB));
- mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB),
- DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE/MiB),
- 0, BLOCK_SHIFT, ATTR_BLOCK | attrs[policy].value);
+ printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n", start_mb * MiB,
+ (start_mb + size_mb) * MiB, attrs[policy].name);
+ assert(start_mb + size_mb <= 4 * (GiB / MiB));
+ mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE / MiB),
+ DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE / MiB), 0, BLOCK_SHIFT,
+ ATTR_BLOCK | attrs[policy].value);
}
/*
@@ -247,24 +244,22 @@
table[0] = ATTR_UNUSED;
if (CONFIG(ARM_LPAE)) {
- pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB);
+ pte_t *const pgd_buff = (pte_t *)(_ttb + 16 * KiB);
pte_t *pmd = ttb_buff;
int i;
- printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n",
- ttb_buff);
+ printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", ttb_buff);
ASSERT((read_mmfr0() & 0xf) >= 5);
/*
* Set MAIR
* See B4.1.104 of ARMv7 Architecture Reference Manual
*/
- write_mair0(
- 0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered,
+ write_mair0(0x00 << (MAIR_INDX_NC * 8) | /* Strongly-ordered,
* Non-Cacheable */
- 0xaa << (MAIR_INDX_WT*8) | /* Write-Thru,
+ 0xaa << (MAIR_INDX_WT * 8) | /* Write-Thru,
* Read-Allocate */
- 0xff << (MAIR_INDX_WB*8) /* Write-Back,
+ 0xff << (MAIR_INDX_WB * 8) /* Write-Back,
* Read/Write-Allocate */
);
@@ -274,8 +269,7 @@
* See B3.6.1 of ARMv7 Architecture Reference Manual
*/
for (i = 0; i < 4; i++) {
- pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) |
- ATTR_NEXTLEVEL;
+ pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | ATTR_NEXTLEVEL;
pmd += BLOCK_SIZE / PAGE_SIZE;
}
@@ -299,10 +293,9 @@
* See B4.1.153 of ARMv7 Architecture Reference Manual
* See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.
*/
- write_ttbcr(
- CONFIG(ARM_LPAE) << 31 |/* EAE. 1:Enable LPAE */
- 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */
- );
+ write_ttbcr(CONFIG(ARM_LPAE) << 31 | /* EAE. 1:Enable LPAE */
+ 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */
+ );
/* Set domain 0 to Client so XN bit works (to prevent prefetches) */
write_dacr(0x5);
diff --git a/src/arch/arm/clock.c b/src/arch/arm/clock.c
index 8855c75..f1f1fe14 100644
--- a/src/arch/arm/clock.c
+++ b/src/arch/arm/clock.c
@@ -5,5 +5,5 @@
void set_cntfrq(uint32_t freq)
{
- __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq));
+ __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" ::"r"(freq));
}
diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c
index 849fc65..79c38cc 100644
--- a/src/arch/arm/eabi_compat.c
+++ b/src/arch/arm/eabi_compat.c
@@ -45,11 +45,9 @@
/* Support the alias for the __aeabi_memclr which may
assume memory alignment. */
-void __aeabi_memclr4(void *dest, size_t n)
- __attribute((alias("__aeabi_memclr")));
+void __aeabi_memclr4(void *dest, size_t n) __attribute((alias("__aeabi_memclr")));
-void __aeabi_memclr8(void *dest, size_t n)
- __attribute((alias("__aeabi_memclr")));
+void __aeabi_memclr8(void *dest, size_t n) __attribute((alias("__aeabi_memclr")));
/* Support the routine __aeabi_memclr. */
void __aeabi_memclr(void *dest, size_t n);
diff --git a/src/arch/arm/fit_payload.c b/src/arch/arm/fit_payload.c
index 19f46a8..46019f5 100644
--- a/src/arch/arm/fit_payload.c
+++ b/src/arch/arm/fit_payload.c
@@ -28,9 +28,7 @@
}
bool fit_payload_arch(struct prog *payload, struct fit_config_node *config,
- struct region *kernel,
- struct region *fdt,
- struct region *initrd)
+ struct region *kernel, struct region *fdt, struct region *initrd)
{
void *arg = NULL;
diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c
index 0c68fc7..4fc63e9 100644
--- a/src/arch/arm/tables.c
+++ b/src/arch/arm/tables.c
@@ -17,8 +17,8 @@
if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
return;
- bootmem_add_range((uintptr_t)_postram_cbfs_cache,
- REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);
+ bootmem_add_range((uintptr_t)_postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache),
+ BM_MEM_RAMSTAGE);
}
void lb_arch_add_records(struct lb_header *header)
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