[coreboot-gerrit] Patch set updated for coreboot: b5e8562 cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generator

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10158

-gerrit

commit b5e8562ec8c2a42872a893b8e3d8b9d9050106f9
Author: Timothy Pearson 
Date:   Fri May 8 17:17:44 2015 -0500

cpu/amd/model_10xxx: Determine single-link status of each CPU in _PSD generator

The prior ACPI _PSD generator committed in ef33db01 incorrectly assumed the active
    link count of each processor was identical.  Detect the link count on each node
    when generating the _PSD objects.

Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf9b
    Signed-off-by: Timothy Pearson 
---
 src/cpu/amd/model_10xxx/powernow_acpi.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/powernow_acpi.c b/src/cpu/amd/model_10xxx/powernow_acpi.c
index db428d3..98ef08a 100644
--- a/src/cpu/amd/model_10xxx/powernow_acpi.c
+++ b/src/cpu/amd/model_10xxx/powernow_acpi.c
@@ -145,7 +145,10 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
    printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);

uint32_t dtemp;
+	uint8_t node_index;
    uint8_t node_count;
+	uint8_t cores_per_node;
+	uint8_t total_core_count;

/*
     * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
@@ -161,9 +164,10 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
    /* Get number of nodes */
    dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60);
    node_count = ((dtemp & 0x70) >> 4) + 1;
+	cores_per_node = cmp_cap + 1;
+
    /* Compute total number of cores installed in system */
-	cmp_cap++;
-	cmp_cap *= node_count;
+	total_core_count = cores_per_node * node_count;

Pstate_num = 0;

@@ -191,10 +195,6 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
    uint32_t core_voltage;	/* multiplied by 10000 */
    uint8_t single_link;

-	/* Determine if this is a single-link system */
-	dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x80);
-	single_link = !!(((dtemp & 0xff00) >> 8) == 0);
-
    /* Determine if this is a PVI or SVI system */
    dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);

@@ -297,9 +297,15 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
    char pscope[] = "\_PR";

acpigen_write_scope(pscope);
-	for (index = 0; index < cmp_cap; index++)
+	for (index = 0; index < total_core_count; index++) {
+		/* Determine if this is a single-link processor */
+		node_index = 0x18 + (index / cores_per_node);
+		dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80);
+		single_link = !!(((dtemp & 0xff00) >> 8) == 0);
+
    	write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_power,
    			Pstate_latency, Pstate_control, Pstate_status,
    			index, pcontrol_blk, plen, onlyBSP, single_link);
+	}
    acpigen_pop_len();
 }