[coreboot-gerrit] Change in coreboot[master]: mediatek/mt8192: memlayout: Add DRAM DMA region

[Roger Lu (Code Review)]

Hello Roger Lu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/47352

to review the following change.

Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region
......................................................................

mediatek/mt8192: memlayout: Add DRAM DMA region

SPM DMA hardware requires a non-cacheable buffer to load SPM
firmware.

TEST=verified with SPM WIP patch.
     SPM PC stays at 0x3f4 after SPM firmware is loaded.

Change-Id: Ic6521f3d14044c01ddd4da8c04126621f18ad32a
---
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/include/soc/memlayout.ld
M src/soc/mediatek/mt8192/mmu_operations.c
3 files changed, 17 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/47352/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 257b636..c7d26f9 100755
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -31,7 +31,7 @@
 romstage-y += emi.c
 romstage-y += flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
-romstage-y += ../common/mmu_operations.c
+romstage-y += ../common/mmu_operations.c mmu_operations.c
 romstage-y += memory.c dramc_param.c ../common/memory_test.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index 891b782..a1c1be6 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -14,6 +14,11 @@
 #define DRAM_INIT_CODE(addr, size) \
    REGION(dram_init_code, addr, size, 4)

+#define DRAM_DMA(addr, size) \
+	REGION(dram_dma, addr, size, 4K) \
+	_ = ASSERT(size % 4K == 0, \
+		"DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
 SECTIONS
 {
    SRAM_START(0x00100000)
@@ -37,8 +42,9 @@
    SRAM_L2C_END(0x00280000)

DRAM_START(0x40000000)
-	POSTRAM_CBFS_CACHE(0x40000000, 2M)
-	RAMSTAGE(0x40200000, 512K)
+	DRAM_DMA(0x40000000, 1M)
+	POSTRAM_CBFS_CACHE(0x40100000, 2M)
+	RAMSTAGE(0x40300000, 512K)

BL31(0x54600000, 0x60000)
 }
diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c
index fb3620e..e3bc622 100644
--- a/src/soc/mediatek/mt8192/mmu_operations.c
+++ b/src/soc/mediatek/mt8192/mmu_operations.c
@@ -3,6 +3,7 @@
 #include <device/mmio.h>
 #include <soc/mcucfg.h>
 #include <soc/mmu_operations.h>
+#include <soc/symbols.h>

DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
 DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
@@ -28,3 +29,10 @@
    		MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
    dsb();
 }
+
+/* mtk_soc_after_dram is called in romstage */
+void mtk_soc_after_dram(void)
+{
+	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
+			 NONSECURE_UNCACHED_MEM);
+}