Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7166
-gerrit
commit 1338a84d7133d5388ca9976b675e40b63b2f849e Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Wed Oct 22 22:03:49 2014 +1100
northbridge: Don't hide pointers behind typedefs
Change-Id: Ib2c373695820e71a6e41e4f173d2615ee5838f28 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/emulation/qemu-i440fx/northbridge.c | 10 +-- src/northbridge/amd/agesa/00730F01/northbridge.c | 70 +++++++++---------- src/northbridge/amd/agesa/family10/northbridge.c | 80 +++++++++++----------- src/northbridge/amd/agesa/family10/reset_test.h | 4 +- src/northbridge/amd/agesa/family12/amdfam12_conf.c | 12 ++-- src/northbridge/amd/agesa/family12/northbridge.c | 50 +++++++------- src/northbridge/amd/agesa/family12/northbridge.h | 2 +- src/northbridge/amd/agesa/family14/amdfam14_conf.c | 12 ++-- src/northbridge/amd/agesa/family14/northbridge.c | 54 +++++++-------- src/northbridge/amd/agesa/family14/northbridge.h | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 72 +++++++++---------- src/northbridge/amd/agesa/family15/northbridge.h | 2 +- src/northbridge/amd/agesa/family15tn/iommu.c | 4 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 66 +++++++++--------- src/northbridge/amd/agesa/family16kb/northbridge.c | 70 +++++++++---------- src/northbridge/amd/amdfam10/northbridge.c | 73 ++++++++++---------- src/northbridge/amd/amdk8/northbridge.c | 64 ++++++++--------- src/northbridge/amd/cimx/rd890/late.c | 2 +- src/northbridge/amd/gx1/northbridge.c | 12 ++-- src/northbridge/amd/gx2/northbridge.c | 12 ++-- src/northbridge/amd/lx/northbridge.c | 12 ++-- src/northbridge/dmp/vortex86ex/northbridge.c | 6 +- src/northbridge/intel/e7501/northbridge.c | 6 +- src/northbridge/intel/e7505/northbridge.c | 8 +-- src/northbridge/intel/e7520/northbridge.c | 16 ++--- src/northbridge/intel/e7525/northbridge.c | 16 ++--- src/northbridge/intel/fsp_rangeley/northbridge.c | 20 +++--- .../intel/fsp_sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/gm45/northbridge.c | 12 ++-- src/northbridge/intel/haswell/northbridge.c | 30 ++++---- src/northbridge/intel/i3100/northbridge.c | 18 ++--- src/northbridge/intel/i440bx/northbridge.c | 8 +-- src/northbridge/intel/i440lx/northbridge.c | 8 +-- src/northbridge/intel/i5000/northbridge.c | 14 ++-- src/northbridge/intel/i82810/northbridge.c | 8 +-- src/northbridge/intel/i82830/northbridge.c | 8 +-- src/northbridge/intel/i855/northbridge.c | 8 +-- src/northbridge/intel/i945/northbridge.c | 14 ++-- src/northbridge/intel/nehalem/northbridge.c | 14 ++-- src/northbridge/intel/sandybridge/northbridge.c | 16 ++--- src/northbridge/intel/sch/northbridge.c | 14 ++-- src/northbridge/rdc/r8610/northbridge.c | 6 +- src/northbridge/via/cn400/northbridge.c | 16 ++--- src/northbridge/via/cn700/northbridge.c | 10 +-- src/northbridge/via/cx700/northbridge.c | 8 +-- src/northbridge/via/vt8601/northbridge.c | 8 +-- src/northbridge/via/vt8623/northbridge.c | 14 ++-- src/northbridge/via/vx800/northbridge.c | 8 +-- src/northbridge/via/vx900/northbridge.c | 14 ++-- src/northbridge/via/vx900/sata.c | 16 ++--- 50 files changed, 523 insertions(+), 522 deletions(-)
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 2714052..b1967de 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -46,7 +46,7 @@ static void qemu_reserve_ports(struct device *dev, unsigned int idx, IORESOURCE_ASSIGNED; }
-static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -213,7 +213,7 @@ static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long * return len; }
-static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int qemu_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = qemu_get_smbios_data16(*handle, current); @@ -234,15 +234,15 @@ static struct device_operations pci_domain_ops = { #endif };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); }
-static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +static unsigned int cpu_bus_scan(struct device * bus, unsigned int max) { int max_cpus = fw_cfg_max_cpus(); - device_t cpu; + struct device * cpu; int i;
if (max_cpus < 0) diff --git a/src/northbridge/amd/agesa/00730F01/northbridge.c b/src/northbridge/amd/agesa/00730F01/northbridge.c index 03433af..06fe3f6 100644 --- a/src/northbridge/amd/agesa/00730F01/northbridge.c +++ b/src/northbridge/amd/agesa/00730F01/northbridge.c @@ -58,15 +58,15 @@ typedef struct dram_base_mask {
static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; }
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); }
-static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; }
-static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -287,7 +287,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; }
-static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource;
@@ -329,7 +329,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
-static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -342,7 +342,7 @@ static void read_resources(device_t dev) } }
-static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -393,7 +393,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */
-static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link;
@@ -402,7 +402,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); }
-static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -449,11 +449,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -499,7 +499,7 @@ struct chip_operations northbridge_amd_agesa_00730F01_ops = { .enable_dev = 0, };
-static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg;
@@ -512,7 +512,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -559,7 +559,7 @@ static void domain_read_resources(device_t dev) #endif }
-static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -663,7 +663,7 @@ static void setup_uma_memory(void) }
-static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -840,13 +840,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] }
-static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -882,12 +882,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; }
-static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -983,7 +983,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus;
@@ -1068,7 +1068,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id);
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1076,12 +1076,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); }
-static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1092,7 +1092,7 @@ static void cpu_bus_read_resources(device_t dev) #endif }
-static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b1f0890..bc4a25d 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -52,10 +52,10 @@ typedef struct dram_base_mask {
struct amdfam10_sysconf_t sysconf; -static device_t __f0_dev[NODE_NUMS]; -static device_t __f1_dev[NODE_NUMS]; -static device_t __f2_dev[NODE_NUMS]; -static device_t __f4_dev[NODE_NUMS]; +static struct device * __f0_dev[NODE_NUMS]; +static struct device * __f1_dev[NODE_NUMS]; +static struct device * __f2_dev[NODE_NUMS]; +static struct device * __f4_dev[NODE_NUMS]; static unsigned fx_devs = 0;
#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 @@ -64,7 +64,7 @@ static unsigned fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0];
@@ -96,7 +96,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -149,7 +149,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, #endif
#if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, +static u32 check_segn(struct device * dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { //check segbusn here, We need every node have the same segn @@ -249,7 +249,7 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, sysconf.mmio_addr_num = index+1; }
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) {
@@ -318,7 +318,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; }
- device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first @@ -357,7 +357,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi #endif }
-static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -407,7 +407,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -415,7 +415,7 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device * dev) { #if NODE_NUMS == 64 unsigned busn; @@ -442,7 +442,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
}
-static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -450,7 +450,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -470,7 +470,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -505,7 +505,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; }
-static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -541,7 +541,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link return resource; }
-static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource;
@@ -600,7 +600,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } }
-static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -612,7 +612,7 @@ static void amdfam10_read_resources(device_t dev) } }
-static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -667,7 +667,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */
-static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link;
@@ -676,7 +676,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -696,7 +696,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); }
-static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -723,12 +723,12 @@ static void mcf0_control_init(struct device *dev) { }
-static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0xff;
nodeid = amdfam10_nodeid(dev); @@ -770,7 +770,7 @@ struct chip_operations northbridge_amd_agesa_family10_ops = { };
-static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device * dev) { unsigned reg;
@@ -783,7 +783,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -829,7 +829,7 @@ static void amdfam10_domain_read_resources(device_t dev) #endif }
-static void amdfam10_domain_enable_resources(device_t dev) +static void amdfam10_domain_enable_resources(struct device * dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); @@ -904,7 +904,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif
-static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1071,7 +1071,7 @@ static void amdfam10_domain_set_resources(device_t dev) } }
-static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1102,7 +1102,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1132,7 +1132,7 @@ static struct device_operations pci_domain_ops = { };
-static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1150,7 +1150,7 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); }
-static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1186,12 +1186,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; }
-static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int nodes; @@ -1282,7 +1282,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus;
@@ -1363,7 +1363,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j);
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1371,12 +1371,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); }
-static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1387,7 +1387,7 @@ static void cpu_bus_read_resources(device_t dev) #endif }
-static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/agesa/family10/reset_test.h b/src/northbridge/amd/agesa/family10/reset_test.h index 8c8d9a0..a38cde8 100644 --- a/src/northbridge/amd/agesa/family10/reset_test.h +++ b/src/northbridge/amd/agesa/family10/reset_test.h @@ -33,7 +33,7 @@ static inline u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -42,7 +42,7 @@ static inline u32 warm_reset_detect(u8 nodeid) static inline void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/northbridge/amd/agesa/family12/amdfam12_conf.c b/src/northbridge/amd/agesa/family12/amdfam12_conf.c index 00ff641..116a466 100644 --- a/src/northbridge/amd/agesa/family12/amdfam12_conf.c +++ b/src/northbridge/amd/agesa/family12/amdfam12_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t {
static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device * dev;
#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; }
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) {
@@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; }
- device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 94de010..7d1b118 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -41,14 +41,14 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1
-static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs=0;
-device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -89,7 +89,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -98,7 +98,7 @@ static void f1_write_config32(unsigned reg, u32 value) }
-static u32 amdfam12_nodeid(device_t dev) +static u32 amdfam12_nodeid(struct device * dev) { printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); return (dev->path.pci.devfn >> 3) - CONFIG_CDB; @@ -108,7 +108,7 @@ static u32 amdfam12_nodeid(device_t dev) #include "amdfam12_conf.c"
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -128,7 +128,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) }
-static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -137,7 +137,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -158,7 +158,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam12_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 result, reg; @@ -182,7 +182,7 @@ static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsi return resource; }
-static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam12_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -218,7 +218,7 @@ static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link }
-static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam12_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource;
@@ -343,7 +343,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif
-static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void read_resources(device_t dev) }
-static void set_resource(device_t dev, struct resource *resource, +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -412,10 +412,10 @@ static void set_resource(device_t dev, struct resource *resource,
#if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif
-static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link;
@@ -447,7 +447,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) }
-static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -503,7 +503,7 @@ static void setup_uma_memory(void)
/* Domain/Root Complex related code */
-static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg;
@@ -518,7 +518,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -581,7 +581,7 @@ static void domain_read_resources(device_t dev) }
-static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -765,7 +765,7 @@ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); }
-static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
@@ -783,7 +783,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */
-static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
@@ -797,7 +797,7 @@ static void cpu_bus_read_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); }
-static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058);
@@ -809,7 +809,7 @@ static void cpu_bus_set_resources(device_t dev) printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/agesa/family12/northbridge.h b/src/northbridge/amd/agesa/family12/northbridge.h index 4edb525..c3fc171 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.h +++ b/src/northbridge/amd/agesa/family12/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops;
-device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn);
#endif /* NORTHBRIDGE_AMD_AGESA_FAM12H_H */ diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index c255213..b72b21b 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -28,7 +28,7 @@ struct dram_base_mask_t {
static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; struct dram_base_mask_t d; #if defined(__PRE_RAM__) dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); @@ -53,7 +53,7 @@ static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) { - device_t dev; + struct device * dev; u32 i; u32 tempreg; u32 index_min, index_max; @@ -115,7 +115,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; u32 tempreg; - device_t dev; + struct device * dev;
#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { @@ -161,7 +161,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 io_min, u32 io_max, u32 nodes) { u32 i; - device_t dev; + struct device * dev; #if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif @@ -222,7 +222,7 @@ static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) return 0; }
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) {
@@ -279,7 +279,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi return; }
- device_t dev; + struct device * dev; u32 j; // if ht_c_index > 3, We should use extend space // for nodeid at first diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 57502e9..de1465b 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -44,13 +44,13 @@ //#define FX_DEVS NODE_NUMS #define FX_DEVS 1
-static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs = 0;
-device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { if ((CONFIG_CDB + nodeid) < 32) { return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); @@ -88,7 +88,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for (i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -96,14 +96,14 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdfam14_nodeid(device_t dev) +static u32 amdfam14_nodeid(struct device * dev) { return (dev->path.pci.devfn >> 3) - CONFIG_CDB; }
#include "amdfam14_conf.c"
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Northbridge init\n"); } @@ -119,7 +119,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
}
-static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -127,7 +127,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -146,7 +146,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, +static struct resource *amdfam14_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; @@ -173,7 +173,7 @@ static struct resource *amdfam14_find_iopair(device_t dev, unsigned nodeid, return resource; }
-static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, +static struct resource *amdfam14_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; @@ -208,7 +208,7 @@ static struct resource *amdfam14_find_mempair(device_t dev, u32 nodeid, return resource; }
-static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam14_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource;
@@ -332,7 +332,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif
-static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) #endif }
-static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -409,10 +409,10 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) }
#if CONFIG_CONSOLE_VGA_MULTI -extern device_t vga_pri; // the primary vga device, defined in device.c +extern struct device * vga_pri; // the primary vga device, defined in device.c #endif
-static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link;
@@ -444,7 +444,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); }
-static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -477,7 +477,7 @@ static void nb_set_resources(device_t dev)
/* Domain/Root Complex related code */
-static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg;
@@ -492,7 +492,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg < 0xc0) { // mmio nodeid = (limit & 0xf) + (base & 0x30); } else { // io @@ -566,7 +566,7 @@ static void setup_uma_memory(void) #endif }
-static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev); @@ -757,7 +757,7 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n"); }
-static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { #if CONFIG_AMD_SB_CIMX if (!acpi_is_wakeup_s3()) { @@ -779,18 +779,18 @@ static void domain_enable_resources(device_t dev)
/* Bus related code */
-static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { }
-static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { }
-static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus = dev->link_list; - device_t cpu; + struct device * cpu; int apic_id, cores_found;
/* There is only one node for fam14, but there may be multiple cores. */ @@ -809,7 +809,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.h b/src/northbridge/amd/agesa/family14/northbridge.h index 474e74c..6046137 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.h +++ b/src/northbridge/amd/agesa/family14/northbridge.h @@ -23,6 +23,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops;
-device_t get_node_pci(u32 nodeid, u32 fn); +struct device * get_node_pci(u32 nodeid, u32 fn);
#endif /* NORTHBRIDGE_AMD_AGESA_FAM14H_H */ diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index ce9785e..c7a141f 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -57,16 +57,16 @@ typedef struct dram_base_mask {
static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -82,7 +82,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; }
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -120,7 +120,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); }
-static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -163,7 +163,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -171,7 +171,7 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -206,7 +206,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -214,7 +214,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -234,7 +234,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -261,7 +261,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; }
-static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -288,7 +288,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link }
-static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource;
@@ -332,7 +332,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) }
-static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -360,7 +360,7 @@ static void nb_read_resources(device_t dev) }
-static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -412,7 +412,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */
-static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link;
@@ -422,7 +422,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -443,7 +443,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) }
-static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -476,11 +476,11 @@ static void northbridge_init(struct device *dev) { }
-static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { @@ -526,7 +526,7 @@ struct chip_operations northbridge_amd_agesa_family15_ops = { .enable_dev = 0, };
-static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg;
@@ -540,7 +540,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -588,7 +588,7 @@ static void domain_read_resources(device_t dev) #endif }
-static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); @@ -681,7 +681,7 @@ static void setup_uma_memory(void) #endif }
-static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -860,13 +860,13 @@ static struct device_operations pci_domain_ops = { };
-static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] }
-static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -902,12 +902,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; }
-static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -987,7 +987,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus;
@@ -1079,7 +1079,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id);
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1087,16 +1087,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); }
-static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { }
-static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { }
@@ -1136,7 +1136,7 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { };
/* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max) { max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); return max; diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h index 99fdcae..3a90964 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.h +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -22,6 +22,6 @@
static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max); +static unsigned int f15_pci_domain_scan_bus(struct device * dev, unsigned int max);
#endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */ diff --git a/src/northbridge/amd/agesa/family15tn/iommu.c b/src/northbridge/amd/agesa/family15tn/iommu.c index 3765f20..5b3529b 100644 --- a/src/northbridge/amd/agesa/family15tn/iommu.c +++ b/src/northbridge/amd/agesa/family15tn/iommu.c @@ -23,7 +23,7 @@ #include <device/pci_ops.h> #include <lib.h>
-static void iommu_read_resources(device_t dev) +static void iommu_read_resources(struct device * dev) { struct resource *res;
@@ -39,7 +39,7 @@ static void iommu_read_resources(device_t dev) res->flags = IORESOURCE_MEM; }
-static void iommu_set_resources(device_t dev) +static void iommu_set_resources(struct device * dev) { struct resource *res;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index d77897d..5f0cafc 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask {
static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; }
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); }
-static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdfam15_nodeid(device_t dev) +static u32 amdfam15_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exist, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam15_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsi return resource; }
-static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam15_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link return resource; }
-static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam15_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource;
@@ -328,7 +328,7 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
-static void nb_read_resources(device_t dev) +static void nb_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -354,7 +354,7 @@ static void nb_read_resources(device_t dev) #endif }
-static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -405,7 +405,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */
-static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link;
@@ -414,7 +414,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -434,7 +434,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); }
-static void nb_set_resources(device_t dev) +static void nb_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -494,7 +494,7 @@ struct chip_operations northbridge_amd_agesa_family15tn_ops = { .enable_dev = 0, };
-static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg;
@@ -507,7 +507,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -554,7 +554,7 @@ static void domain_read_resources(device_t dev) #endif }
-static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -647,7 +647,7 @@ static void setup_uma_memory(void) }
-static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -824,13 +824,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] }
-static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -866,12 +866,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; }
-static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -951,7 +951,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus;
@@ -1041,7 +1041,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id);
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1049,16 +1049,16 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); }
-static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { }
-static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { }
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d47a00d..cc79da3 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -57,15 +57,15 @@ typedef struct dram_base_mask {
static unsigned node_nums; static unsigned sblink; -static device_t __f0_dev[MAX_NODE_NUMS]; -static device_t __f1_dev[MAX_NODE_NUMS]; -static device_t __f2_dev[MAX_NODE_NUMS]; -static device_t __f4_dev[MAX_NODE_NUMS]; +static struct device * __f0_dev[MAX_NODE_NUMS]; +static struct device * __f1_dev[MAX_NODE_NUMS]; +static struct device * __f2_dev[MAX_NODE_NUMS]; +static struct device * __f4_dev[MAX_NODE_NUMS]; static unsigned fx_devs = 0;
static dram_base_mask_t get_dram_base_mask(u32 nodeid) { - device_t dev; + struct device * dev; dram_base_mask_t d; dev = __f1_dev[0]; u32 temp; @@ -81,7 +81,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; }
-static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, +static void set_io_addr_reg(struct device * dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { u32 i; @@ -119,7 +119,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi pci_write_config32(__f1_dev[i], reg, tempreg); }
-static device_t get_node_pci(u32 nodeid, u32 fn) +static struct device * get_node_pci(u32 nodeid, u32 fn) { #if MAX_NODE_NUMS + CONFIG_CDB >= 32 if ((CONFIG_CDB + nodeid) < 32) { @@ -162,7 +162,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -170,7 +170,7 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdfam16_nodeid(device_t dev) +static u32 amdfam16_nodeid(struct device * dev) { #if MAX_NODE_NUMS == 64 unsigned busn; @@ -205,7 +205,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) * @retval 0 resource exists, not usable * @retval 1 resource exist, resource has been allocated before */ -static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -213,7 +213,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -233,7 +233,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam16_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -260,7 +260,7 @@ static struct resource *amdfam16_find_iopair(device_t dev, unsigned nodeid, unsi return resource; }
-static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam16_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -286,7 +286,7 @@ static struct resource *amdfam16_find_mempair(device_t dev, u32 nodeid, u32 link return resource; }
-static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam16_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource;
@@ -328,7 +328,7 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link)
}
-static void read_resources(device_t dev) +static void read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -341,7 +341,7 @@ static void read_resources(device_t dev) } }
-static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +static void set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; unsigned reg, link_num; @@ -392,7 +392,7 @@ static void set_resource(device_t dev, struct resource *resource, u32 nodeid) * but it is too difficult to deal with the resource allocation magic. */
-static void create_vga_resource(device_t dev, unsigned nodeid) +static void create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link;
@@ -401,7 +401,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -421,7 +421,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, sblink); }
-static void set_resources(device_t dev) +static void set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -448,11 +448,11 @@ static void northbridge_init(struct device *dev) { } #if 0 /* TODO: Check if needed. */ -static unsigned scan_chains(device_t dev, unsigned max) +static unsigned scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; - device_t io_hub = NULL; + struct device * io_hub = NULL; u32 next_unitid = 0x18; nodeid = amdfam16_nodeid(dev); if (nodeid == 0) { @@ -498,7 +498,7 @@ struct chip_operations northbridge_amd_agesa_family16kb_ops = { .enable_dev = 0, };
-static void domain_read_resources(device_t dev) +static void domain_read_resources(struct device * dev) { unsigned reg;
@@ -511,7 +511,7 @@ static void domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if (reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -558,7 +558,7 @@ static void domain_read_resources(device_t dev) #endif }
-static void domain_enable_resources(device_t dev) +static void domain_enable_resources(struct device * dev) { if (acpi_is_wakeup_s3()) AGESAWRAPPER(fchs3laterestore); @@ -653,7 +653,7 @@ static void setup_uma_memory(void) }
-static void domain_set_resources(device_t dev) +static void domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -830,13 +830,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] }
-static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -872,12 +872,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; }
-static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int coreid_bits; @@ -957,7 +957,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) /* Find which cpus are present */ cpu_bus = dev->link_list; for (i = 0; i < node_nums; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus;
@@ -1047,7 +1047,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id);
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1055,12 +1055,12 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); }
-static void cpu_bus_read_resources(device_t dev) +static void cpu_bus_read_resources(struct device * dev) { #if CONFIG_MMCONF_SUPPORT struct resource *resource = new_resource(dev, 0xc0010058); @@ -1071,7 +1071,7 @@ static void cpu_bus_read_resources(device_t dev) #endif }
-static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 76ffc5d..8b87abc 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -53,13 +53,13 @@ struct amdfam10_sysconf_t sysconf;
#define FX_DEVS NODE_NUMS -static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; -static device_t __f2_dev[FX_DEVS]; -static device_t __f4_dev[FX_DEVS]; +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; +static struct device * __f2_dev[FX_DEVS]; +static struct device * __f4_dev[FX_DEVS]; static unsigned fx_devs=0;
-device_t get_node_pci(u32 nodeid, u32 fn) +struct device * get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS + CONFIG_CDB >= 32 if((CONFIG_CDB + nodeid) < 32) { @@ -102,7 +102,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -110,7 +110,7 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdfam10_nodeid(device_t dev) +static u32 amdfam10_nodeid(struct device * dev) { #if NODE_NUMS == 64 unsigned busn; @@ -139,7 +139,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
}
-static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdfam10_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) { // I want to put sb chain in bus 0 can I? @@ -152,7 +152,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l u32 max_bus; u32 min_bus; u32 is_sublink1 = (link_num>3); - device_t devx; + struct device * devx; u32 busses; u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 @@ -284,7 +284,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l return max; }
-static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static unsigned amdfam10_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -327,7 +327,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) }
-static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -335,7 +335,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -355,7 +355,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static struct resource *amdfam10_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource; u32 free_reg, reg; @@ -389,7 +389,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi return resource; }
-static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link) +static struct resource *amdfam10_find_mempair(struct device * dev, u32 nodeid, u32 link) { struct resource *resource; u32 free_reg, reg; @@ -425,7 +425,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link }
-static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) +static void amdfam10_link_read_bases(struct device * dev, u32 nodeid, u32 link) { struct resource *resource;
@@ -484,7 +484,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) } }
-static void amdfam10_read_resources(device_t dev) +static void amdfam10_read_resources(struct device * dev) { u32 nodeid; struct bus *link; @@ -496,7 +496,7 @@ static void amdfam10_read_resources(device_t dev) } }
-static void amdfam10_set_resource(device_t dev, struct resource *resource, +static void amdfam10_set_resource(struct device * dev, struct resource *resource, u32 nodeid) { resource_t rbase, rend; @@ -551,7 +551,7 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource, * but it is too difficult to deal with the resource allocation magic. */
-static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) +static void amdfam10_create_vga_resource(struct device * dev, unsigned nodeid) { struct bus *link;
@@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -580,7 +580,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) set_vga_enable_reg(nodeid, link->link_num); }
-static void amdfam10_set_resources(device_t dev) +static void amdfam10_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -629,7 +629,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = { .enable_dev = 0, };
-static void amdfam10_domain_read_resources(device_t dev) +static void amdfam10_domain_read_resources(struct device * dev) { unsigned reg;
@@ -642,7 +642,7 @@ static void amdfam10_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io @@ -767,7 +767,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device * dev; struct dram_base_mask_t d; u32 sel_m; u32 sel_hi_en; @@ -871,7 +871,7 @@ static void setup_uma_memory(void) #endif }
-static void amdfam10_domain_set_resources(device_t dev) +static void amdfam10_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1087,7 +1087,7 @@ static void amdfam10_domain_set_resources(device_t dev) } }
-static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static u32 amdfam10_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1118,7 +1118,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1146,7 +1146,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void sysconf_init(device_t dev) // first node +static void sysconf_init(struct device * dev) // first node { sysconf.sblk = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 sysconf.segbit = 0; @@ -1188,7 +1188,7 @@ static void sysconf_init(device_t dev) // first node #endif }
-static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1224,12 +1224,12 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; }
-static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; #if CONFIG_CBB - device_t pci_domain; + struct device * pci_domain; #endif int i,j; int nodes; @@ -1324,7 +1324,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus);
for(i = 0; i < nodes; i++) { - device_t cdb_dev; + struct device * cdb_dev; unsigned busn, devn; struct bus *pbus;
@@ -1394,7 +1394,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } } #endif - device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1402,7 +1402,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX @@ -1411,11 +1411,12 @@ static void cpu_bus_init(device_t dev) #endif }
-static void cpu_bus_read_resources(device_t dev) + +static void cpu_bus_read_resources(struct device * dev) { }
-static void cpu_bus_set_resources(device_t dev) +static void cpu_bus_set_resources(struct device * dev) { struct resource *resource = find_resource(dev, 0xc0010058); if (resource) { diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index a91a499..816d9e4 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -40,8 +40,8 @@ struct amdk8_sysconf_t sysconf;
#define MAX_FX_DEVS 8 -static device_t __f0_dev[MAX_FX_DEVS]; -static device_t __f1_dev[MAX_FX_DEVS]; +static struct device * __f0_dev[MAX_FX_DEVS]; +static struct device * __f1_dev[MAX_FX_DEVS]; static unsigned fx_devs=0;
static void get_fx_devs(void) @@ -71,7 +71,7 @@ static void f1_write_config32(unsigned reg, u32 value) if (fx_devs == 0) get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t dev; + struct device * dev; dev = __f1_dev[i]; if (dev && dev->enabled) { pci_write_config32(dev, reg, value); @@ -79,12 +79,12 @@ static void f1_write_config32(unsigned reg, u32 value) } }
-static u32 amdk8_nodeid(device_t dev) +static u32 amdk8_nodeid(struct device * dev) { return (dev->path.pci.devfn >> 3) - 0x18; }
-static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, +static u32 amdk8_scan_chain(struct device * dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink, u32 max, u32 offset_unitid) {
@@ -232,7 +232,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link return max; }
-static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static unsigned amdk8_scan_chains(struct device * dev, unsigned max) { unsigned nodeid; struct bus *link; @@ -271,7 +271,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) }
-static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, +static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { struct resource *res; @@ -279,7 +279,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, int result; res = 0; for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; + struct device * dev; dev = __f0_dev[nodeid]; if (!dev) continue; @@ -299,7 +299,7 @@ static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, return result; }
-static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, +static unsigned amdk8_find_reg(struct device * dev, unsigned nodeid, unsigned link, unsigned min, unsigned max) { unsigned resource; @@ -327,17 +327,17 @@ static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link, return resource; }
-static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8); }
-static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link) +static unsigned amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) { return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8); }
-static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) +static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) { struct resource *resource;
@@ -376,9 +376,9 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link) } }
-static void amdk8_create_vga_resource(device_t dev, unsigned nodeid); +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid);
-static void amdk8_read_resources(device_t dev) +static void amdk8_read_resources(struct device * dev) { unsigned nodeid; struct bus *link; @@ -391,7 +391,7 @@ static void amdk8_read_resources(device_t dev) amdk8_create_vga_resource(dev, nodeid); }
-static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid) +static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) { struct bus *link; resource_t rbase, rend; @@ -488,7 +488,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned report_resource_stored(dev, resource, buf); }
-static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) { struct resource *resource; struct bus *link; @@ -498,7 +498,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_MULTIPLE_VGA_ADAPTERS - extern device_t vga_pri; // the primary vga device, defined in device.c + extern struct device * vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ @@ -529,7 +529,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) IORESOURCE_ASSIGNED; }
-static void amdk8_set_resources(device_t dev) +static void amdk8_set_resources(struct device * dev) { unsigned nodeid; struct bus *bus; @@ -638,7 +638,7 @@ struct chip_operations northbridge_amd_amdk8_ops = { .enable_dev = 0, };
-static void amdk8_domain_read_resources(device_t dev) +static void amdk8_domain_read_resources(struct device * dev) { unsigned reg;
@@ -651,7 +651,7 @@ static void amdk8_domain_read_resources(device_t dev) /* Is this register allocated? */ if ((base & 3) != 0) { unsigned nodeid, reg_link; - device_t reg_dev; + struct device * reg_dev; nodeid = limit & 7; reg_link = (limit >> 4) & 3; reg_dev = __f0_dev[nodeid]; @@ -765,7 +765,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void disable_hoist_memory(unsigned long hole_startk, int node_id) { int i; - device_t dev; + struct device * dev; u32 base, limit; u32 hoist; u32 hole_sizek; @@ -810,7 +810,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) { int i; u32 carry_over; - device_t dev; + struct device * dev; u32 base, limit; u32 basek; u32 hoist; @@ -904,7 +904,7 @@ static void setup_uma_memory(void) #endif }
-static void amdk8_domain_set_resources(device_t dev) +static void amdk8_domain_set_resources(struct device * dev) { #if CONFIG_PCI_64BIT_PREF_MEM struct resource *io, *mem1, *mem2; @@ -1121,7 +1121,7 @@ static void amdk8_domain_set_resources(device_t dev)
}
-static u32 amdk8_domain_scan_bus(device_t dev, u32 max) +static u32 amdk8_domain_scan_bus(struct device * dev, u32 max) { u32 reg; int i; @@ -1136,7 +1136,7 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) */ get_fx_devs(); for(i = 0; i < fx_devs; i++) { - device_t f0_dev; + struct device * f0_dev; f0_dev = __f0_dev[i]; if (f0_dev && f0_dev->enabled) { u32 httc; @@ -1164,7 +1164,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void add_more_links(device_t dev, unsigned total_links) +static void add_more_links(struct device * dev, unsigned total_links) { struct bus *link, *last = NULL; int link_num; @@ -1200,10 +1200,10 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; }
-static u32 cpu_bus_scan(device_t dev, u32 max) +static u32 cpu_bus_scan(struct device * dev, u32 max) { struct bus *cpu_bus; - device_t dev_mc; + struct device * dev_mc; int bsp_apicid; int i,j; unsigned nb_cfg_54; @@ -1258,7 +1258,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) remap_bsp_lapic(cpu_bus);
for(i = 0; i < sysconf.nodes; i++) { - device_t cpu_dev; + struct device * cpu_dev;
/* Find the cpu's pci device */ cpu_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); @@ -1267,7 +1267,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) * ensure all of the cpu's pci devices are found. */ int local_j; - device_t dev_f0; + struct device * dev_f0; for(local_j = 0; local_j <= 3; local_j++) { cpu_dev = pci_probe_dev(NULL, dev_mc->bus, PCI_DEVFN(0x18 + i, local_j)); @@ -1334,7 +1334,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) } }
- device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + struct device * cpu = add_cpu_device(cpu_bus, apic_id, enable_node); if (cpu) amd_cpu_topology(cpu, i, j); } //j @@ -1342,7 +1342,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) return max; }
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { #if CONFIG_WAIT_BEFORE_CPUS_INIT cpus_ready_for_init(); diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index fa23344..09cdce5 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -66,7 +66,7 @@ void nb_Late_Post_Init(void) LibSystemApiCall(AmdLatePostInit, &gConfig); }
-static void rd890_enable(device_t dev) +static void rd890_enable(struct device * dev) { u32 address = 0; u32 devfn; diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index bcb6e56..d960406 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -14,7 +14,7 @@ /* */
-static void optimize_xbus(device_t dev) +static void optimize_xbus(struct device * dev) { /* Optimise X-Bus performance */ pci_write_config8(dev, 0x40, 0x1e); @@ -31,13 +31,13 @@ static void optimize_xbus(device_t dev) * this region? **/
-static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { write32(GX_BASE+BC_XMAP_2, 0x77777777); write32(GX_BASE+BC_XMAP_3, 0x77777777); }
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
@@ -65,9 +65,9 @@ static const struct pci_driver northbridge_driver __pci_driver = {
#include <cbmem.h>
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -126,7 +126,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__); initialize_cpus(dev->link_list); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..e7a37f1 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -213,12 +213,12 @@ int sizeram(void) return sizem; }
-static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) {
}
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__);
@@ -273,11 +273,11 @@ static const struct pci_driver northbridge_driver __pci_driver = {
#include <cbmem.h>
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { int idx; u32 tomk; - device_t mc_dev; + struct device * mc_dev;
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
@@ -296,7 +296,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
-static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
@@ -318,7 +318,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..9a75fc4 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -291,11 +291,11 @@ int sizeram(void) return sizem; }
-static void enable_shadow(device_t dev) +static void enable_shadow(struct device * dev) { }
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { //msr_t msr;
@@ -372,11 +372,11 @@ static const struct pci_driver northbridge_driver __pci_driver = {
#include <cbmem.h>
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { int idx; u32 tomk; - device_t mc_dev; + struct device * mc_dev;
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
@@ -395,7 +395,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
-static void pci_domain_enable(device_t dev) +static void pci_domain_enable(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
@@ -422,7 +422,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index fcebed8..e193168 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -30,7 +30,7 @@
#define SPI_BASE 0xfc00
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_DEBUG, "Vortex86EX northbridge early init ...\n"); // enable F0A/ECA/E8A/E4A/E0A/C4A/C0A shadow read/writable. @@ -75,9 +75,9 @@ static void set_cmos_memory_size(unsigned long sizek) * don't touch it. */ }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n"); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 64bf840..407df57 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -20,9 +20,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -110,7 +110,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08cd023..0f6a1ce 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -16,9 +16,9 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -97,7 +97,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -117,7 +117,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 6e0379e..42c2f84 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -15,9 +15,9 @@
static unsigned int max_bus;
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
-static u32 e7520_domain_scan_bus(device_t dev, u32 max) +static u32 e7520_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -122,7 +122,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource;
@@ -134,7 +134,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource;
@@ -145,7 +145,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -170,7 +170,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x3590, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -184,7 +184,7 @@ static struct device_operations cpu_bus_ops = { };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 68fdc74..b6cb7fc 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -15,9 +15,9 @@
static unsigned int max_bus;
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -106,7 +106,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
-static u32 e7525_domain_scan_bus(device_t dev, u32 max) +static u32 e7525_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -121,7 +121,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource;
@@ -133,7 +133,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource;
@@ -144,7 +144,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -169,7 +169,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x359e, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -183,7 +183,7 @@ static struct device_operations cpu_bus_ops = { };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 07ce21f..04cb5d9 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -63,7 +63,7 @@ static const int legacy_hole_size_k = 384;
static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg;
*base = 0; @@ -112,7 +112,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; }
-static void finalize_dev (device_t dev) +static void finalize_dev (struct device * dev) { /* * Notify FSP for PostPciEnumeration. @@ -123,7 +123,7 @@ static void finalize_dev (device_t dev) printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); }
-static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device * dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; u64 bmbound_hi; @@ -168,7 +168,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); }
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -177,7 +177,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* * Assign memory resources for PCI devices @@ -187,13 +187,13 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { /* Call the normal set_resources */ pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -208,7 +208,7 @@ static void northbridge_init(struct device *dev) { }
-static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { }
@@ -258,7 +258,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = pci_device_ids, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -271,7 +271,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index da27b25..e6f1fec 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -68,7 +68,7 @@ static const int legacy_hole_size_k = 384;
static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg;
*base = 0; @@ -121,7 +121,7 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -261,7 +261,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource;
@@ -283,7 +283,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource;
@@ -297,7 +297,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -322,7 +322,7 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); }
-static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -375,7 +375,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -388,7 +388,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 716ee62..b7737aa 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -46,7 +46,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) *base = 0; *len = 0;
- const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0;
@@ -73,7 +73,7 @@ static int decode_pcie_bar(u32 *const base, u32 *const len) return 0; }
-static void mch_domain_read_resources(device_t dev) +static void mch_domain_read_resources(struct device * dev) { u64 tom, touud; u32 tomk, tolud, uma_sizek = 0, usable_tomk; @@ -170,7 +170,7 @@ static void mch_domain_read_resources(device_t dev) } }
-static void mch_domain_set_resources(device_t dev) +static void mch_domain_set_resources(struct device * dev) { struct resource *resource; int i; @@ -185,7 +185,7 @@ static void mch_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
-static void mch_domain_init(device_t dev) +static void mch_domain_init(struct device * dev) { u32 reg32;
@@ -207,7 +207,7 @@ static struct device_operations pci_domain_ops = { };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -221,7 +221,7 @@ static struct device_operations cpu_bus_ops = { };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..1cd6ac0 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -39,7 +39,7 @@ #include "chip.h" #include "haswell.h"
-static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg;
@@ -69,7 +69,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -87,7 +87,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 bar;
@@ -106,7 +106,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device * dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -126,7 +126,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device * dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -146,7 +146,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device * dev) { int i;
@@ -203,7 +203,7 @@ struct map_entry { const char *description; };
-static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device * dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -272,7 +272,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), };
-static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device * dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -280,7 +280,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } }
-static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device * dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -291,7 +291,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); }
-static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device * dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -383,7 +383,7 @@ static void mc_add_dram_resources(device_t dev) #endif }
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -395,7 +395,7 @@ static void mc_read_resources(device_t dev) mc_add_dram_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -433,7 +433,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; }
-static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; @@ -480,7 +480,7 @@ static const struct pci_driver mc_driver_hsw_ult __pci_driver = { .device = PCI_DEVICE_ID_HSW_ULT, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { bsp_init_and_start_aps(dev->link_list); } @@ -493,7 +493,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 2cf5ae1..8f30486 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -39,9 +39,9 @@ static u32 max_bus;
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -132,7 +132,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); }
-static u32 i3100_domain_scan_bus(device_t dev, u32 max) +static u32 i3100_domain_scan_bus(struct device * dev, u32 max) { max_bus = pci_domain_scan_bus(dev, max); return max_bus; @@ -147,7 +147,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource;
@@ -159,7 +159,7 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource;
@@ -170,7 +170,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); @@ -180,7 +180,7 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device * dev; u64 mmcfg;
dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_MC, 0); // 0:0x13.0 @@ -219,7 +219,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = PCI_DEVICE_ID_INTEL_3100_MC, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -233,7 +233,7 @@ static struct device_operations cpu_bus_ops = { };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 12ff37b..866a778 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -12,7 +12,7 @@ #include "northbridge.h" #include "i440bx.h"
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -32,9 +32,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, };
-static void i440bx_domain_set_resources(device_t dev) +static void i440bx_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -81,7 +81,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 60e62c1..4070c7a 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -38,7 +38,7 @@ * Maciej */
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge Init\n"); } @@ -58,9 +58,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, };
-static void i440lx_domain_set_resources(device_t dev) +static void i440lx_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -107,7 +107,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index a9b3560..30517bb 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -29,7 +29,7 @@ #include <arch/acpi.h> #include <cbmem.h>
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -40,15 +40,15 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } }
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource; uint32_t hecbase, amsize, tolm; uint64_t ambase, memsize; int idx = 0;
- device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); - device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1)); + struct device * dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); + struct device * dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
pci_dev_read_resources(dev);
@@ -139,7 +139,7 @@ static const struct pci_driver mc_driver __pci_driver = { .devices = nb_ids, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -151,7 +151,7 @@ static struct device_operations cpu_bus_ops = { .init = cpu_bus_init, .scan_bus = 0, }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -165,7 +165,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index ce0dc20..5925e63 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -32,7 +32,7 @@ #include "northbridge.h" #include "i82810.h"
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -69,9 +69,9 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, };
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0;
@@ -136,7 +136,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 4898aaf..a317613 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -30,7 +30,7 @@ #include <string.h> #include "i82830.h"
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -50,9 +50,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, };
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; int igd_memory = 0; uint64_t uma_memory_base = 0, uma_memory_size = 0;
@@ -103,7 +103,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index fce7d57..ff3ca5b 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -32,7 +32,7 @@ #include <cpu/x86/cache.h> #include <cpu/cpu.h>
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "Northbridge init\n"); } @@ -52,9 +52,9 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, };
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); @@ -119,7 +119,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 91c5c82..494253f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -33,7 +33,7 @@
static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg;
*base = 0; @@ -81,7 +81,7 @@ static void add_fixed_resources(struct device *dev, int index) } }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint32_t pci_tolm; uint8_t tolud, reg8; @@ -185,7 +185,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource;
@@ -207,7 +207,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource;
@@ -221,7 +221,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -274,7 +274,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x27a0, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -287,7 +287,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..ea14c12 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -96,7 +96,7 @@ static void add_fixed_resources(struct device *dev, int index) #endif }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { assign_resources(dev->link_list); } @@ -114,7 +114,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { uint32_t tseg_base; uint64_t TOUUD; @@ -165,13 +165,13 @@ static void mc_read_resources(device_t dev) add_fixed_resources(dev, 10); }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { /* And call the normal set_resources */ pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -283,7 +283,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; }
-static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -324,7 +324,7 @@ static const struct pci_driver mc_driver_44 __pci_driver = { .device = 0x0044, /* Nehalem */ };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -337,7 +337,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..ab28093 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -66,7 +66,7 @@ static const int legacy_hole_size_k = 384;
static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg;
*base = 0; @@ -132,7 +132,7 @@ static void add_fixed_resources(struct device *dev, int index) bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -266,7 +266,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource;
@@ -288,7 +288,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource;
@@ -302,7 +302,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -412,7 +412,7 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; }
-static void northbridge_enable(device_t dev) +static void northbridge_enable(struct device * dev) { #if CONFIG_HAVE_ACPI_RESUME switch (pci_read_config32(dev, SKPAD)) { @@ -471,7 +471,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -484,7 +484,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index c552879..e2cc496 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -33,7 +33,7 @@
static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device * dev; u32 pciexbar_reg;
dev = dev_find_slot(0, PCI_DEVFN(0, 0)); @@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { u32 pci_tolm; u8 reg8; @@ -200,7 +200,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device * dev) { struct resource *resource;
@@ -226,7 +226,7 @@ static void mc_read_resources(device_t dev) (unsigned long)(resource->base + resource->size)); }
-static void mc_set_resources(device_t dev) +static void mc_set_resources(struct device * dev) { struct resource *resource;
@@ -239,7 +239,7 @@ static void mc_set_resources(device_t dev) pci_dev_set_resources(dev); }
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -292,7 +292,7 @@ static const struct pci_driver mc_driver __pci_driver = { .device = 0x8100, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -305,7 +305,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index d69c4f6..5ca0ab3 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -33,7 +33,7 @@
static unsigned long get_memory_size(void) { - device_t nb_dev; + struct device * nb_dev; u8 size;
nb_dev = dev_find_device(PCI_VENDOR_ID_RDC, @@ -42,7 +42,7 @@ static unsigned long get_memory_size(void) return (2 * 1024) << size; }
-static void cpu_pci_domain_set_resources(device_t dev) +static void cpu_pci_domain_set_resources(struct device * dev) { u32 pci_tolm = find_pci_tolm(dev->link_list); unsigned long tomk = 0, tolmk; @@ -92,7 +92,7 @@ static int rdc_get_smbios_data16(int handle, unsigned long *current) return len; }
-static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current) +static int rdc_get_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len; len = rdc_get_smbios_data16(*handle, current); diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index b797179..dc64991 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn400.h"
-static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { - device_t vlink_dev; + struct device * vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg, reg8; int i, j; @@ -140,7 +140,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, };
-static void cn400_domain_read_resources(device_t dev) +static void cn400_domain_read_resources(struct device * dev) { struct resource *resource;
@@ -162,7 +162,7 @@ static void cn400_domain_read_resources(device_t dev) }
#ifdef UNUSED_CODE -static void ram_reservation(device_t dev, unsigned long index, +static void ram_reservation(struct device * dev, unsigned long index, unsigned long base, unsigned long size) { struct resource *res; @@ -177,9 +177,9 @@ static void ram_reservation(device_t dev, unsigned long index, } #endif
-static void cn400_domain_set_resources(device_t dev) +static void cn400_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm;
printk(BIOS_SPEW, "Entering %s.\n", __func__); @@ -219,7 +219,7 @@ static void cn400_domain_set_resources(device_t dev) printk(BIOS_SPEW, "Leaving %s.\n", __func__); }
-static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max) +static unsigned int cn400_domain_scan_bus(struct device * dev, unsigned int max) { printk(BIOS_DEBUG, "Entering %s.\n", __func__);
@@ -236,7 +236,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 506bdd1..c1bd74c 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -34,9 +34,9 @@ #include "northbridge.h" #include "cn700.h"
-static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { - device_t vlink_dev; + struct device * vlink_dev; u16 reg16; u8 ranks, pagec, paged, pagee, pagef, shadowreg;
@@ -97,11 +97,11 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, };
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* The order is important to find the correct RAM size. */ static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm;
printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); @@ -156,7 +156,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index cc9dabd..bb8caf9 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -31,9 +31,9 @@ #include <cbmem.h> #include <arch/acpi.h>
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; unsigned char reg; unsigned long tomk, tolmk; @@ -82,7 +82,7 @@ static void pci_domain_set_resources(device_t dev)
unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device * dev; u64 mmcfg;
dev = dev_find_device(0x1106, 0x324b, 0); // 0:0x13.0 @@ -112,7 +112,7 @@ static struct device_operations pci_domain_ops = { .write_acpi_tables = acpi_write_hpet, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 1887491..2565b1d 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -17,7 +17,7 @@ * slower than normal, ethernet drops packets). * Apparently these registers govern some sort of bus master behavior. */ -static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { printk(BIOS_SPEW, "VT8601 random fixup ...\n"); pci_write_config8(dev, 0x70, 0xc0); @@ -44,12 +44,12 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ };
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); @@ -102,7 +102,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 546db4c..0b5030b 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -19,9 +19,9 @@ * Apparently these registers govern some sort of bus master behavior. */
-static void northbridge_init(device_t dev) +static void northbridge_init(struct device * dev) { - device_t fb_dev; + struct device * fb_dev; unsigned long fb; unsigned char c;
@@ -58,7 +58,7 @@ static void northbridge_init(device_t dev) } }
-static void nullfunc(device_t dev) +static void nullfunc(struct device * dev) { /* Nothing to do */ } @@ -76,7 +76,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8623, };
-static void agp_init(device_t dev) +static void agp_init(struct device * dev) { printk(BIOS_DEBUG, "VT8623 AGP random fixup ...\n");
@@ -103,10 +103,10 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, };
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; - device_t mc_dev; + struct device * mc_dev; uint32_t pci_tolm;
printk(BIOS_SPEW, "Entering vt8623 pci_domain_set_resources.\n"); @@ -162,7 +162,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index fad0c2f..e0fb06f 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -37,7 +37,7 @@ /* !!FIXME!! I declared this to fix the build. */ u8 acpi_sleep_type = 0;
-static void memctrl_init(device_t dev) +static void memctrl_init(struct device * dev) { /* set VGA in uma_ram_setting.c, not in this function. @@ -71,13 +71,13 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, };
-static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device * dev) { /* * the order is important to find the correct ram size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - device_t mc_dev; + struct device * mc_dev; u32 pci_tolm; u8 reg;
@@ -145,7 +145,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index f9c225d..7047a04 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -60,7 +60,7 @@ uint64_t get_uma_memory_base(void) return uma_memory_base; }
-static u64 vx900_get_top_of_ram(device_t mcu) +static u64 vx900_get_top_of_ram(struct device * mcu) { u16 reg16; /* The last valid DRAM address is computed by the MCU @@ -97,7 +97,7 @@ static void killme_debug_4g_remap_reg(u32 reg32) * * @return The new top of memory. */ -static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) +static u64 vx900_remap_above_4g(struct device * mcu, u32 tolm) { size_t i; u8 reg8, start8, end8, start, end; @@ -216,7 +216,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm) return newtor; }
-static void vx900_set_resources(device_t dev) +static void vx900_set_resources(struct device * dev) { u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
@@ -228,7 +228,7 @@ static void vx900_set_resources(device_t dev) "========================================\n");
int idx = 10; - const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA, + struct device * mcu = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0); if (!mcu) { @@ -286,7 +286,7 @@ static void vx900_set_resources(device_t dev) assign_resources(dev->link_list); }
-static void vx900_read_resources(device_t dev) +static void vx900_read_resources(struct device * dev) { /* Our fixed resources start at 0 */ int idx = 0; @@ -317,7 +317,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, };
-static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device * dev) { initialize_cpus(dev->link_list); } @@ -330,7 +330,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
-static void enable_dev(device_t dev) +static void enable_dev(struct device * dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index 63295e5..4a7ae6d 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -74,7 +74,7 @@ static void vx900_print_sata_errors(u32 flags) print_debug("\tUNRECOGNIZED FIS type\n"); }
-static void vx900_dbg_sata_errors(device_t dev) +static void vx900_dbg_sata_errors(struct device *dev) { /* Port 0 */ if (pci_read_config8(dev, 0xa0) & (1 << 0)) { @@ -103,7 +103,7 @@ static sata_phy_config reference_ephy = { 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, };
-static u32 sata_phy_read32(device_t dev, u8 index) +static u32 sata_phy_read32(struct device *dev, u8 index) { /* The SATA PHY control registers are accessed by a funny index/value * scheme. Each byte (0,1,2,3) has its own 4-bit index */ @@ -115,7 +115,7 @@ static u32 sata_phy_read32(device_t dev, u8 index) return pci_read_config32(dev, 0x64); }
-static void sata_phy_write32(device_t dev, u8 index, u32 val) +static void sata_phy_write32(struct device *dev, u8 index, u32 val) { /* The SATA PHY control registers are accessed by a funny index/value * scheme. Each byte (0,1,2,3) has its own 4-bit index */ @@ -127,7 +127,7 @@ static void sata_phy_write32(device_t dev, u8 index, u32 val) pci_write_config32(dev, 0x64, val); }
-static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) +static void vx900_sata_read_phy_config(struct device *dev, sata_phy_config cfg) { size_t i; u32 *data = (u32 *) cfg; @@ -136,7 +136,7 @@ static void vx900_sata_read_phy_config(device_t dev, sata_phy_config cfg) } }
-static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg) +static void vx900_sata_write_phy_config(struct device *dev, sata_phy_config cfg) { size_t i; u32 *data = (u32 *) cfg; @@ -181,7 +181,7 @@ static void vx900_sata_dump_phy_config(sata_phy_config cfg) * Our only option is to operate in IDE mode. We choose native IDE so that we * can freely assign an IRQ, and are not forced to use IRQ14 */ -static void vx900_native_ide_mode(device_t dev) +static void vx900_native_ide_mode(struct device *dev) { /* Disable subclass write protect */ pci_mod_config8(dev, 0x45, 1 << 7, 0); @@ -193,7 +193,7 @@ static void vx900_native_ide_mode(device_t dev) pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); }
-static void vx900_sata_init(device_t dev) +static void vx900_sata_init(struct device *dev) { /* Enable SATA primary channel IO access */ pci_mod_config8(dev, 0x40, 0, 1 << 1); @@ -261,7 +261,7 @@ static void vx900_sata_init(device_t dev) vx900_dbg_sata_errors(dev); }
-static void vx900_sata_read_resources(device_t dev) +static void vx900_sata_read_resources(struct device *dev) { pci_dev_read_resources(dev); }