Patch Set 3: Code-Review-1

I don't think this is correct. It is hardcoding mainboard information about USB ports in SoC code.

Thanks. We will move con0 and con1 from SoC to platform.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52
Gerrit-Change-Number: 38777
Gerrit-PatchSet: 3
Gerrit-Owner: John Zhao <john.zhao@intel.com>
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Gerrit-Comment-Date: Thu, 13 Feb 2020 02:32:56 +0000
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