Rizwan Qureshi uploaded patch set #3 to this change.

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mb/google/hatch: Change the DEVSLP reset config to PLTRST

In S3 the PCH is driving the DEVSLP signal low, assuming that the SATA device
is already powered off. However on hatch the SATA power is still enabled. And,
since DEVSLP is low, this causes the SATA device to not enter low power state.
The fix here is to set the pad config to be reset on PLTRST assertion which
will cause the pin to be high impedance state and will be pulled up by the
SATA device.

BUG=b:126611255
BRANCH=None
TEST=Make sure that S3 and S0ix is working fine on hatch.
And also make sure that DEVSLP is pulled high in S3.

Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/32136/3

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981
Gerrit-Change-Number: 32136
Gerrit-PatchSet: 3
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: newpatchset