huayang duan has uploaded this change for review.
mediatek/mt8183: enable DDR low power feature
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test pass on Kukui.
Change-Id: Ic48580e7e5db25dc1c29dabf41c4e3816fb946d3
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com
---
M src/soc/mediatek/mt8183/dramc_pi_basic_api.c
M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
M src/soc/mediatek/mt8183/emi.c
M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
M src/soc/mediatek/mt8183/include/soc/dramc_register.h
M src/soc/mediatek/mt8183/include/soc/emi.h
6 files changed, 132 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32010/1
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
index 3ca5c22..15771ee 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
@@ -154,9 +154,6 @@
for (size_t r = 0; r < 2; r++)
for (size_t b = 0; b < 2; b++) {
- /* Track rising and update rising/falling together */
- clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2],
- 0x1 << 29);
clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7],
(0x3f << 0) | (0x3f << 8) |
(0x7f << 16) | (0x7f << 24),
@@ -172,8 +169,6 @@
(0x3 << 18) | (0x3 << 16));
}
- clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24));
-
/* Rx DLY tracking setting (Static) */
clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0],
(0x1 << 29) | (0xf << 4) | (0x1 << 0),
@@ -181,6 +176,7 @@
clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0],
(0x1 << 29) | (0xf << 4) | (0x1 << 0),
(0x1 << 29) | (0x0 << 4) | (0x1 << 0));
+ clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24));
for (u8 b = 0; b < 2; b++) {
clrsetbits_le32(&ch[chn].phy.b[b].dq[9],
@@ -201,10 +197,12 @@
static void dramc_hw_dqs_gating_tracking(u8 chn)
{
- setbits_le32(&ch[chn].ao.stbcal, (0x3 << 26) | (0x1 << 0));
+ clrsetbits_le32(&ch[chn].ao.stbcal,
+ (0x1 << 21) | (0x3 << 15) | (0x1f << 8) | (0x1 << 4),
+ (0x3 << 26) | (0x1 << 0));
clrsetbits_le32(&ch[chn].ao.stbcal1,
(0xffff << 16) | (0x1 << 8) | (0x1 << 6),
- (0x1 << 16) | (0x1 << 8) | (0x0 << 6));
+ (0x1 << 16) | (0x1 << 8) | (0x1 << 6));
clrsetbits_le32(&ch[chn].phy.misc_ctrl0,
(0x1 << 24) | (0x1f << 11) | (0xf << 0),
@@ -262,6 +260,72 @@
dramc_set_broadcast(broadcast_bak);
}
+
+static void DramcDummyReadForTrackingEnable(u8 chn)
+{
+ setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 16);
+
+ for (size_t r = 0; r < 2; r++)
+ for (size_t i = 0; i < 4; i++)
+ write32(&ch[chn].ao.rk[r].dummy_rd_wdata[i],
+ 0xaaaa5555);
+
+ clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
+ for (size_t r = 0; r < 2; r++) {
+ clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr,
+ (0x1ffff << 0) | (0x7ff << 17) | (0xf << 28),
+ (0x7fff << 0) | (0x3f0 << 17));
+ setbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0);
+ }
+
+ clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20);
+}
+
+static void SetCKE2RankIndependent(u8 chn)
+{
+ clrsetbits_le32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2);
+ clrsetbits_le32(&ch[chn].ao.ckectrl,
+ (0x1 << 1) | (0xf << 8) | (0x7 << 13),
+ (0x4 << 8) | (0x2 << 13));
+
+ for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
+ setbits_le32(&ch[chn].ao.shu[shu].conf[2],
+ (0x1 << 29) | (0x1 << 31));
+ clrbits_le32(&ch[chn].ao.dramctrl, 0x1 << 9);
+}
+
+static void dramc_pa_improve(u8 chn)
+{
+ clrbits_le32(&ch[chn].ao.clkar, 0xffff);
+ clrbits_le32(&ch[chn].ao.srefctrl, 0xf << 12);
+ clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19);
+ clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
+ clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19);
+ clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
+
+ for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
+ clrbits_le32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2);
+}
+
+static void dramc_set_mr13_vrcg_to_Normal(u8 chn)
+{
+ for (u8 rank = 0; rank < RANK_MAX; rank++)
+ dramc_mode_reg_write_by_rank(chn, rank, 13, 0xd0);
+
+ for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
+ clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19);
+}
+
+static void dramc_enable_dramc_dcm(void)
+{
+ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
+ clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl,
+ (0x7 << 0) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31),
+ (0x7 << 0) | (0x1 << 30) | (0x1 << 31));
+ setbits_le32(&ch[chn].ao.clkar, 0x1 << 31);
+ }
+}
+
void dramc_runtime_config(void)
{
clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 29);
@@ -270,39 +334,83 @@
transfer_pll_to_spm_control();
setbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 25);
+ dramc_show("%s with: broadcast %d\n", __func__, dramc_get_broadcast());
+
+
+ /* RX_TRACKING: ON */
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
dramc_rx_input_delay_tracking(chn);
+ /* HW_GATING: ON */
dramc_hw_gating_init();
dramc_hw_gating_onoff(CHANNEL_A, true);
+ dramc_hw_gating_onoff(CHANNEL_B, true);
+ /* HW_GATING DBG: OFF */
for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
clrbits_le32(&ch[chn].ao.stbcal2,
(0x3 << 4) | (0x3 << 8) | (0x1 << 28));
+ /* DUMMY_READ_FOR_TRACKING: ON */
+ for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
+ DramcDummyReadForTrackingEnable(chn);
+
+ /* ZQCS_ENABLE_LP4: ON */
clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30);
clrbits_le32(&ch[1].ao.spcmdctrl, 0x1 << 30);
+ /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */
dramc_phy_low_power_enable();
dramc_enable_phy_dcm(true);
+ /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */
for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry,
(0x1 << 1) | (0x3 << 13));
+ /* SPM_CONTROL_AFTERK: ON */
write32(&ch[0].phy.misc_spm_ctrl0, 0xfbffefff);
write32(&ch[1].phy.misc_spm_ctrl0, 0xfbffefff);
write32(&ch[0].phy.misc_spm_ctrl2, 0xffffffef);
write32(&ch[1].phy.misc_spm_ctrl2, 0x7fffffef);
+ /* IMPEDANCE_TRACKING: ON */
dramc_impedance_tracking_enable();
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
+ /* TEMP_SENSOR: ON */
clrbits_le32(&ch[chn].ao.spcmdctrl, 0x3 << 28);
setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11));
- clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 18);
- setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24);
- setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7);
+
+ /* PER_BANK_REFRESH: ON */
+ clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18);
+
+ /* HW_SAVE_FOR_SR: ON */
+ clrbits_le32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28));
+ setbits_le32(&ch[chn].ao.refctrl1, 0x1 << 0);
+ clrsetbits_le32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22);
+
+ /* SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON */
+ SetCKE2RankIndependent(chn);
+
+ /* CLK_FREE_FUN_FOR_DRAMC_PSEL: ON */
+ clrbits_le32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2));
+ clrbits_le32(&ch[chn].ao.clkar, 0x1 << 19);
+
+ /* PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON */
+ dramc_pa_improve(chn);
+
+ /* DRAM DRS DISABLE */
+ clrsetbits_le32(&ch[chn].ao.drsctrl,
+ (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6),
+ (0x1 << 19) | (0x3 << 12) | (0x8 << 8) |
+ (0x3 << 4) | (0x1 << 2) | (0x1 << 0));
+ setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 26);
+
+ dramc_set_mr13_vrcg_to_Normal(chn);
}
+
+ enable_emi_dcm();
+ dramc_enable_dramc_dcm();
}
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index f3c76a9..11a46bb 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -127,7 +127,7 @@
setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak);
}
-static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank,
+void dramc_mode_reg_write_by_rank(u8 chn, u8 rank,
u8 mr_idx, u8 value)
{
u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK;
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index 757a453..b7d7d7b 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -292,6 +292,15 @@
emi_init2(params);
}
+void enable_emi_dcm(void)
+{
+ clrsetbits_le32(&emi_regs->conm, 0xff << 24, 0x0 << 24);
+ clrsetbits_le32(&emi_regs->conn, 0xff << 24, 0x0 << 24);
+
+ for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
+ clrsetbits_le32(&ch[chn].emi.chn_conb, 0xff << 24, 0x0 << 24);
+}
+
static void do_calib(const struct sdram_params *params)
{
dramc_apply_pre_calibration_config();
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
index 781443a..7e0f34e 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
@@ -127,4 +127,6 @@
void dramc_calibrate_all_channels(const struct sdram_params *params);
void dramc_hw_gating_onoff(u8 chn, bool onoff);
void dramc_enable_phy_dcm(bool bEn);
+void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value);
+
#endif /* _DRAMC_PI_API_MT8183_H */
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_register.h b/src/soc/mediatek/mt8183/include/soc/dramc_register.h
index 2487504..f0720a7 100644
--- a/src/soc/mediatek/mt8183/include/soc/dramc_register.h
+++ b/src/soc/mediatek/mt8183/include/soc/dramc_register.h
@@ -265,10 +265,7 @@
struct dramc_ao_regs_rk {
uint32_t dqsosc;
uint32_t rsvd_1[5];
- uint32_t dummy_rd_wdata0;
- uint32_t dummy_rd_wdata1;
- uint32_t dummy_rd_wdata2;
- uint32_t dummy_rd_wdata3;
+ uint32_t dummy_rd_wdata[4];
uint32_t dummy_rd_adr;
uint32_t dummy_rd_bk;
uint32_t pre_tdqsck[12];
diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h
index 81e3d91..2c04a50 100644
--- a/src/soc/mediatek/mt8183/include/soc/emi.h
+++ b/src/soc/mediatek/mt8183/include/soc/emi.h
@@ -38,6 +38,7 @@
int complex_mem_test(u8 *start, unsigned int len);
size_t sdram_size(void);
const struct sdram_params *get_sdram_config(void);
+void enable_emi_dcm(void);
void mt_set_emi(const struct sdram_params *params);
void mt_mem_init(const struct sdram_params *params);
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