Name of user not set #1003174 has uploaded this change for review.
Zotac AD04: Review session / comments from 2020-11-10
Signed-off-by: moscovium-115 <3134c487@tutanota.com>
Change-Id: I65b3438def4b98609e6dabf588677a7214252b7b
---
M src/mainboard/zotac/ad04/BiosCallOuts.c
M src/mainboard/zotac/ad04/Kconfig
M src/mainboard/zotac/ad04/mainboard.c
M src/mainboard/zotac/ad04/romstage.c
D src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex
D src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex
6 files changed, 23 insertions(+), 602 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47723/1
diff --git a/src/mainboard/zotac/ad04/BiosCallOuts.c b/src/mainboard/zotac/ad04/BiosCallOuts.c
index 4944a85..8c62094 100644
--- a/src/mainboard/zotac/ad04/BiosCallOuts.c
+++ b/src/mainboard/zotac/ad04/BiosCallOuts.c
@@ -9,12 +9,11 @@
#include "gpio_ftns.h"
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_DO_RESET, agesa_Reset },
- {AGESA_READ_SPD, board_ReadSpd_from_cbfs },
+ {AGESA_READ_SPD, agesa_ReadSpd },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess },
@@ -26,33 +25,10 @@
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
/* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
// Make sure the right speed settings are selected.
((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5;
return AGESA_SUCCESS;
}
-
-static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
- AGESA_READ_SPD_PARAMS *info = ConfigPtr;
-
- if (!ENV_ROMSTAGE)
- return AGESA_UNSUPPORTED;
-
- u8 index = get_spd_offset();
-
- if (info->MemChannelId > 0)
- return AGESA_UNSUPPORTED;
- if (info->SocketId != 0)
- return AGESA_UNSUPPORTED;
- if (info->DimmId != 0)
- return AGESA_UNSUPPORTED;
-
- /* Read index 0, first SPD_SIZE bytes of spd.bin file. */
- if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0)
- die("No SPD data\n");
-
- return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/zotac/ad04/Kconfig b/src/mainboard/zotac/ad04/Kconfig
index 4dbf869..4f0f5a3 100644
--- a/src/mainboard/zotac/ad04/Kconfig
+++ b/src/mainboard/zotac/ad04/Kconfig
@@ -17,7 +17,6 @@
select BOARD_ROMSIZE_KB_2048
select HAVE_SPD_IN_CBFS
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
- select MAINBOARD_HAS_LPC_TPM
config MAINBOARD_DIR
string
@@ -25,7 +24,7 @@
config MAINBOARD_PART_NUMBER
string
- default "apu1"
+ default "ad04"
config HW_MEM_HOLE_SIZEK
hex
@@ -60,42 +59,6 @@
bool
default n
-choice
- prompt "J19 pins 1-10"
- default APU1_PINMUX_OFF_C
-
-config APU1_PINMUX_OFF_C
- bool "disable"
-
-config APU1_PINMUX_GPIO0
- bool "GPIO"
-
-config APU1_PINMUX_UART_C
- bool "UART 0x3e8"
-
-endchoice
-
-config UART_C_RS485
- bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C
-
-choice
- prompt "J19 pins 11-20"
- default APU1_PINMUX_OFF_D
-
-config APU1_PINMUX_OFF_D
- bool "disable"
-
-config APU1_PINMUX_GPIO1
- bool "GPIO"
-
-config APU1_PINMUX_UART_D
- bool "UART 0x2e8"
-
-endchoice
-
-config UART_D_RS485
- bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D
-
config DIMM_SPD_SIZE
int
default 128
diff --git a/src/mainboard/zotac/ad04/mainboard.c b/src/mainboard/zotac/ad04/mainboard.c
index 2562765..11228af 100644
--- a/src/mainboard/zotac/ad04/mainboard.c
+++ b/src/mainboard/zotac/ad04/mainboard.c
@@ -121,53 +121,6 @@
*/
#define SIO_PORT 0x2e
-/*
-static void config_gpio_mux(void)
-{
- struct device *uart, *gpio;
-
- uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
- gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
- if (uart)
- uart->enabled = CONFIG(APU1_PINMUX_UART_C);
- if (gpio)
- gpio->enabled = CONFIG(APU1_PINMUX_GPIO0);
-
- uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
- gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
- if (uart)
- uart->enabled = CONFIG(APU1_PINMUX_UART_D);
- if (gpio)
- gpio->enabled = CONFIG(APU1_PINMUX_GPIO1);
-}
-*/
-
-/*
-static void pnp_raw_resource(struct device *dev, u8 reg, u8 val)
-{
- struct resource *res;
- res = new_resource(dev, reg);
- res->base = val;
- res->size = 0;
- res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED;
-}
-*/
-
-/*
-static void config_addon_uart(void)
-{
- struct device *uart;
-
- uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
- if (uart && uart->enabled && CONFIG(UART_C_RS485))
- pnp_raw_resource(uart, 0xf2, 0x12);
-
- uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
- if (uart && uart->enabled && CONFIG(UART_D_RS485))
- pnp_raw_resource(uart, 0xf2, 0x12);
-}
-*/
-
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
@@ -181,7 +134,7 @@
t = (struct smbios_type16 *)*current;
len = sizeof(struct smbios_type16);
memset(t, 0, len);
- max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */
+ max_capacity = 8; // From dmidecode.log
t->type = SMBIOS_PHYS_MEMORY_ARRAY;
t->handle = *handle;
@@ -376,9 +329,9 @@
* LED2/D6/GPIO_190 should be 1
* LED3/D5/GPIO_191 should be 1
*/
- configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
- configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
- configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
+ /* configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); */
+ /* configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); */
+ /* configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); */
usb_oc_setup();
}
diff --git a/src/mainboard/zotac/ad04/romstage.c b/src/mainboard/zotac/ad04/romstage.c
index f594827..0c959a2 100644
--- a/src/mainboard/zotac/ad04/romstage.c
+++ b/src/mainboard/zotac/ad04/romstage.c
@@ -17,23 +17,23 @@
bdata |= 0x05; //set bits 0,2
pm_write8(SB_PMIOA_REG5B, bdata);
- /* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */
- bdata = pm_read8(SB_PMIOA_REGEA);
- bdata &= 0xfe; //clear bit 0
- bdata |= 0x01; //set bit 0
- pm_write8(SB_PMIOA_REGEA, bdata);
+ /* /1* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins *1/ */
+ /* bdata = pm_read8(SB_PMIOA_REGEA); */
+ /* bdata &= 0xfe; //clear bit 0 */
+ /* bdata |= 0x01; //set bit 0 */
+ /* pm_write8(SB_PMIOA_REGEA, bdata); */
- //configure required GPIOs
- configure_gpio(GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
- configure_gpio(GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
- configure_gpio(GPIO_15, GPIO_FTN_1, GPIO_INPUT);
- configure_gpio(GPIO_16, GPIO_FTN_1, GPIO_INPUT);
- configure_gpio(GPIO_17, GPIO_FTN_1, GPIO_INPUT);
- configure_gpio(GPIO_18, GPIO_FTN_1, GPIO_INPUT);
- configure_gpio(GPIO_187, GPIO_FTN_1, GPIO_INPUT);
- configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
- configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
- configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
+ /* //configure required GPIOs */
+ /* configure_gpio(GPIO_10, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); */
+ /* configure_gpio(GPIO_11, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); */
+ /* configure_gpio(GPIO_15, GPIO_FTN_1, GPIO_INPUT); */
+ /* configure_gpio(GPIO_16, GPIO_FTN_1, GPIO_INPUT); */
+ /* configure_gpio(GPIO_17, GPIO_FTN_1, GPIO_INPUT); */
+ /* configure_gpio(GPIO_18, GPIO_FTN_1, GPIO_INPUT); */
+ /* configure_gpio(GPIO_187, GPIO_FTN_1, GPIO_INPUT); */
+ /* configure_gpio(GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); */
+ /* configure_gpio(GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); */
+ /* configure_gpio(GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); */
}
void board_BeforeAgesa(struct sysinfo *cb)
diff --git a/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex b/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex
deleted file mode 100644
index 72377c4..0000000
--- a/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ2G83CFR.spd.hex
+++ /dev/null
@@ -1,234 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# HYNIX-H5TQ2G83CFR
-
-# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down
-# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-# bits[3:0]: 1 = 128 SPD Bytes Used
-# bits[6:4]: 1 = 256 SPD Bytes Total
-# bit7 : 0 = CRC covers bytes 0 ~ 125
-11
-
-# 1 SPD Revision -
-# 0x10 = Revision 1.0
-10
-# 2 Key Byte / DRAM Device Type
-# bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-# 3 Key Byte / Module Type
-# bits[3:0]: 3 = SO-DIMM
-# bits[7:4]: reserved
-03
-
-# 4 SDRAM CHIP Density and Banks
-# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
-# bits[6:4]: 0 = 3 (8 banks)
-# bit7 : reserved
-03
-
-# 5 SDRAM Addressing
-# bits[2:0]: 1 = 10 Column Address Bits
-# bits[5:3]: 3 = 15 Row Address Bits
-# bits[7:6]: reserved
-19
-
-# 6 Module Nominal Voltage, VDD
-# bit0 : 0 = 1.5 V operable
-# bit1 : 0 = NOT 1.35 V operable
-# bit2 : 0 = NOT 1.25 V operable
-# bits[7:3]: reserved
-00
-
-# 7 Module Organization
-# bits[2:0]: 1 = 8 bits
-# bits[5:3]: 0 = 1 Rank
-# bits[7:6]: reserved
-01
-
-# 8 Module Memory Bus Width
-# bits[2:0]: 3 = Primary bus width is 64 bits
-# bits[4:3]: 0 = 0 bits (no bus width extension)
-# bits[7:5]: reserved
-03
-
-# 9 Fine Timebase (FTB) Dividend / Divisor
-# bits[3:0]: 0x01 divisor
-# bits[7:4]: 0x01 dividend
-# 1 / 1 = 1.0 ps
-11
-
-# 10 Medium Timebase (MTB) Dividend
-# 11 Medium Timebase (MTB) Divisor
-# 1 / 8 = .125 ns
-01 08
-
-# 12 SDRAM Minimum Cycle Time (tCKmin)
-# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
-0C
-
-# 13 Reserved
-00
-
-# 14 CAS Latencies Supported, Least Significant Byte
-# 15 CAS Latencies Supported, Most Significant Byte
-# Cas Latencies of 11 - 5 are supported
-7E 00
-
-# 16 Minimum CAS Latency Time (tAAmin)
-# 0x6C = 13.5ns - DDR3-1333
-6C
-
-# 17 Minimum Write Recovery Time (tWRmin)
-# 0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 0x6E = 13.5ns - DDR3-1333
-6C
-
-# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-# 0x30 = 6ns
-30
-
-# 20 Minimum Row Precharge Delay Time (tRPmin)
-# 0x6C = 13.5ns - DDR3-1333
-6C
-
-# 21 Upper Nibbles for tRAS and tRC
-# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-# 0x120 = 36ns - DDR3-1333 (see byte 21)
-20
-
-# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-# 0x28C = 49.5ns - DDR3-1333
-8C
-
-# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-# 0x500 = 160ns - for 2 Gigabit chips
-00 05
-
-# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
-3C
-
-# 28 Upper Nibble for tFAWmin
-# 29 Minimum Four Activate Window Delay Time (tFAWmin)
-# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
-00 F0
-
-# 30 SDRAM Optional Feature
-# bit0 : 1= RZQ/6 supported
-# bit1 : 1 = RZQ/7 supported
-# bits[6:2]: reserved
-# bit7 : 1 = DLL Off mode supported
-83
-
-# 31 SDRAM Thermal and Refresh Options
-# bit0 : 1 = Temp up to 95c supported
-# bit1 : 0 = 85-95c uses 2x refresh rate
-# bit2 : 1 = Auto Self Refresh supported
-# bit3 : 0 = no on die thermal sensor
-# bits[6:4]: reserved
-# bit7 : 0 = partial self refresh supported
-05
-
-# 32 Module Thermal Sensor
-# 0 = Thermal sensor not incorporated onto this assembly
-00
-
-# 33 SDRAM Device Type
-# bits[1:0]: 2 = Signal Loading
-# bits[3:2]: reserved
-# bits[6:4]: 4 = Die count
-# bit7 : 0 = Standard Monolithic DRAM Device
-42
-
-# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-# 39 (reserved)
-00
-
-# 40 - 47 (reserved)
-00 00 00 00 00 00 00 00
-
-# 48 - 55 (reserved)
-00 00 00 00 00 00 00 00
-
-# 56 - 59 (reserved)
-00 00 00 00
-
-# 60 Raw Card Extension, Module Nominal Height
-# bits[4:0]: 0 = <= 15mm tall
-# bits[7:5]: 0 = raw card revision 0-3
-00
-
-# 61 Module Maximum Thickness
-# bits[3:0]: 0 = thickness front <= 1mm
-# bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-# 62 Reference Raw Card Used
-# bits[4:0]: 0 = Reference Raw card A used
-# bits[6:5]: 0 = revision 0
-# bit7 : 0 = Reference raw cards A through AL
-00
-
-# 63 Address Mapping from Edge Connector to DRAM
-# bit0 : 0 = standard mapping (not mirrored)
-# bits[7:1]: reserved
-00
-
-# 64 - 71 (reserved)
-00 00 00 00 00 00 00 00
-
-# 72 - 79 (reserved)
-00 00 00 00 00 00 00 00
-
-# 80 - 87 (reserved)
-00 00 00 00 00 00 00 00
-
-# 88 - 95 (reserved)
-00 00 00 00 00 00 00 00
-
-# 96 - 103 (reserved)
-00 00 00 00 00 00 00 00
-
-# 104 - 111 (reserved)
-00 00 00 00 00 00 00 00
-
-# 112 - 116 (reserved)
-00 00 00 00 00
-
-# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-# 0x0001 = AMD
-00 01
-
-# 119 Module ID: Module Manufacturing Location - oem specified
-00
-
-# 120 Module ID: Module Manufacture Year in BCD
-# 0x13 = 2013
-# 121 Module ID: Module Manufacture week
-# 0x12 = 12th week
-13 12
-
-# 122 - 125: Module Serial Number
-00 00 00 00
-
-# 126 - 127: Cyclical Redundancy Code
-c4 1b
diff --git a/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex b/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex
deleted file mode 100644
index b6d24b4..0000000
--- a/src/mainboard/zotac/ad04/spd/HYNIX-H5TQ4G83MFR.spd.hex
+++ /dev/null
@@ -1,237 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# HYNIX-H5TQ4G83MFR
-
-# SPD contents for APU 2GB DDR3 (1333MHz PC1333) soldered down
-# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-# bits[3:0]: 1 = 128 SPD Bytes Used
-# bits[6:4]: 1 = 256 SPD Bytes Total
-# bit7 : 0 = CRC covers bytes 0 ~ 125
-11
-
-# 1 SPD Revision -
-# 0x10 = Revision 1.0
-10
-# 2 Key Byte / DRAM Device Type
-# bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-# 3 Key Byte / Module Type
-# bits[3:0]: 3 = SO-DIMM
-# bits[7:4]: reserved
-03
-
-# 4 SDRAM CHIP Density and Banks
-# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
-# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
-# bits[6:4]: 0 = 3 (8 banks)
-# bit7 : reserved
-04
-
-# 5 SDRAM Addressing
-# bits[2:0]: 1 = 10 Column Address Bits
-# bits[5:3]: 3 = 15 Row Address Bits
-# bits[5:3]: 4 = 16 Row Address Bits
-# bits[7:6]: reserved
-21
-
-# 6 Module Nominal Voltage, VDD
-# bit0 : 0 = 1.5 V operable
-# bit1 : 0 = NOT 1.35 V operable
-# bit2 : 0 = NOT 1.25 V operable
-# bits[7:3]: reserved
-00
-
-# 7 Module Organization
-# bits[2:0]: 1 = 8 bits
-# bits[5:3]: 0 = 1 Rank
-# bits[7:6]: reserved
-01
-
-# 8 Module Memory Bus Width
-# bits[2:0]: 3 = Primary bus width is 64 bits
-# bits[4:3]: 0 = 0 bits (no bus width extension)
-# bits[7:5]: reserved
-03
-
-# 9 Fine Timebase (FTB) Dividend / Divisor
-# bits[3:0]: 0x01 divisor
-# bits[7:4]: 0x01 dividend
-# 1 / 1 = 1.0 ps
-11
-
-# 10 Medium Timebase (MTB) Dividend
-# 11 Medium Timebase (MTB) Divisor
-# 1 / 8 = .125 ns
-01 08
-
-# 12 SDRAM Minimum Cycle Time (tCKmin)
-# 0x0c = tCKmin of 1.5 ns = in multiples of MTB
-0C
-
-# 13 Reserved
-00
-
-# 14 CAS Latencies Supported, Least Significant Byte
-# 15 CAS Latencies Supported, Most Significant Byte
-# Cas Latencies of 11 - 5 are supported
-7E 00
-
-# 16 Minimum CAS Latency Time (tAAmin)
-# 0x6C = 13.5ns - DDR3-1333
-6C
-
-# 17 Minimum Write Recovery Time (tWRmin)
-# 0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 0x6E = 13.5ns - DDR3-1333
-6C
-
-# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-# 0x30 = 6ns
-30
-
-# 20 Minimum Row Precharge Delay Time (tRPmin)
-# 0x6C = 13.5ns - DDR3-1333
-6C
-
-# 21 Upper Nibbles for tRAS and tRC
-# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-# 0x120 = 36ns - DDR3-1333 (see byte 21)
-20
-
-# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-# 0x28C = 49.5ns - DDR3-1333
-8C
-
-# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-# 0x500 = 160ns - for 2 Gigabit chips
-# 0x820 = 260ns - for 4 Gigabit chips
-20 08
-
-# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
-3C
-
-# 28 Upper Nibble for tFAWmin
-# 29 Minimum Four Activate Window Delay Time (tFAWmin)
-# 0x00F0 = 30ns - DDR3-1333, 1 KB page size
-00 F0
-
-# 30 SDRAM Optional Feature
-# bit0 : 1= RZQ/6 supported
-# bit1 : 1 = RZQ/7 supported
-# bits[6:2]: reserved
-# bit7 : 1 = DLL Off mode supported
-83
-
-# 31 SDRAM Thermal and Refresh Options
-# bit0 : 1 = Temp up to 95c supported
-# bit1 : 0 = 85-95c uses 2x refresh rate
-# bit2 : 1 = Auto Self Refresh supported
-# bit3 : 0 = no on die thermal sensor
-# bits[6:4]: reserved
-# bit7 : 0 = partial self refresh supported
-05
-
-# 32 Module Thermal Sensor
-# 0 = Thermal sensor not incorporated onto this assembly
-00
-
-# 33 SDRAM Device Type
-# bits[1:0]: 2 = Signal Loading
-# bits[3:2]: reserved
-# bits[6:4]: 4 = Die count
-# bit7 : 0 = Standard Monolithic DRAM Device
-42
-
-# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-# 39 (reserved)
-00
-
-# 40 - 47 (reserved)
-00 00 00 00 00 00 00 00
-
-# 48 - 55 (reserved)
-00 00 00 00 00 00 00 00
-
-# 56 - 59 (reserved)
-00 00 00 00
-
-# 60 Raw Card Extension, Module Nominal Height
-# bits[4:0]: 0 = <= 15mm tall
-# bits[7:5]: 0 = raw card revision 0-3
-00
-
-# 61 Module Maximum Thickness
-# bits[3:0]: 0 = thickness front <= 1mm
-# bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-# 62 Reference Raw Card Used
-# bits[4:0]: 0 = Reference Raw card A used
-# bits[6:5]: 0 = revision 0
-# bit7 : 0 = Reference raw cards A through AL
-00
-
-# 63 Address Mapping from Edge Connector to DRAM
-# bit0 : 0 = standard mapping (not mirrored)
-# bits[7:1]: reserved
-00
-
-# 64 - 71 (reserved)
-00 00 00 00 00 00 00 00
-
-# 72 - 79 (reserved)
-00 00 00 00 00 00 00 00
-
-# 80 - 87 (reserved)
-00 00 00 00 00 00 00 00
-
-# 88 - 95 (reserved)
-00 00 00 00 00 00 00 00
-
-# 96 - 103 (reserved)
-00 00 00 00 00 00 00 00
-
-# 104 - 111 (reserved)
-00 00 00 00 00 00 00 00
-
-# 112 - 116 (reserved)
-00 00 00 00 00
-
-# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-# 0x0001 = AMD
-00 01
-
-# 119 Module ID: Module Manufacturing Location - oem specified
-00
-
-# 120 Module ID: Module Manufacture Year in BCD
-# 0x13 = 2013
-# 121 Module ID: Module Manufacture week
-# 0x12 = 12th week
-13 12
-
-# 122 - 125: Module Serial Number
-00 00 00 00
-
-# 126 - 127: Cyclical Redundancy Code
-7b 97
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