Aamir Bohra has uploaded this change for review.
mb/intel/icelake_rvp: Use board ID and spd index from mainboard common
Change-Id: I5d1a8a6da855b7ec2906a135a60ca2902307fd4c
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
---
M src/mainboard/intel/icelake_rvp/Makefile.inc
D src/mainboard/intel/icelake_rvp/board_id.c
D src/mainboard/intel/icelake_rvp/board_id.h
M src/mainboard/intel/icelake_rvp/romstage_fsp_params.c
M src/mainboard/intel/icelake_rvp/spd/spd_util.c
M src/soc/intel/icelake/Kconfig
6 files changed, 4 insertions(+), 91 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/37708/1
diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc
index 74d02cb..c9c817f 100644
--- a/src/mainboard/intel/icelake_rvp/Makefile.inc
+++ b/src/mainboard/intel/icelake_rvp/Makefile.inc
@@ -22,12 +22,10 @@
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += romstage_fsp_params.c
-romstage-y += board_id.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
ramstage-y += mainboard.c
-ramstage-y += board_id.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c
deleted file mode 100644
index c0def22..0000000
--- a/src/mainboard/intel/icelake_rvp/board_id.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include "board_id.h"
-#include <boardid.h>
-#include <ec/acpi/ec.h>
-#include <stdint.h>
-#include <ec/google/chromeec/ec.h>
-
-static int get_board_id_via_ext_ec(void)
-{
- uint32_t id = BOARD_ID_INIT;
-
- if (google_chromeec_get_board_version(&id))
- id = BOARD_ID_UNKNOWN;
-
- return id;
-}
-
-/* Get Board ID via EC I/O port write/read */
-int get_board_id(void)
-{
- MAYBE_STATIC_NONZERO int id = -1;
-
- if (id < 0) {
- if (CONFIG(EC_GOOGLE_CHROMEEC))
- id = get_board_id_via_ext_ec();
- else{
- uint8_t buffer[2];
- uint8_t index;
- if (send_ec_command(EC_FAB_ID_CMD) == 0) {
- for (index = 0; index < sizeof(buffer); index++)
- buffer[index] = recv_ec_data();
- id = (buffer[0] << 8) | buffer[1];
- }
- }
- }
-
- return id;
-}
diff --git a/src/mainboard/intel/icelake_rvp/board_id.h b/src/mainboard/intel/icelake_rvp/board_id.h
deleted file mode 100644
index 3ccfe37..0000000
--- a/src/mainboard/intel/icelake_rvp/board_id.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _MAINBOARD_BOARD_ID_H_
-#define _MAINBOARD_BOARD_ID_H_
-
-/* Board/FAB ID Command */
-#define EC_FAB_ID_CMD 0x0D
-
-/*
- * Returns board information (board id[15:8] and
- * Fab info[7:0]) on success and < 0 on error
- */
-int get_board_id(void);
-
-#endif /* _MAINBOARD_BOARD_ID_H_ */
diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c
index 5a4d681..5db6f18 100644
--- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c
@@ -15,15 +15,15 @@
#include <console/console.h>
#include <fsp/api.h>
+#include <intel_mb/spd.h>
#include <soc/romstage.h>
#include <spd_bin.h>
-#include "board_id.h"
#include "spd/spd.h"
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
- u8 spd_index = (get_board_id() & 0x1F) & 0x7;
+ u8 spd_index = get_spd_index();
printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index);
if (spd_index > 0 && spd_index != 2) {
diff --git a/src/mainboard/intel/icelake_rvp/spd/spd_util.c b/src/mainboard/intel/icelake_rvp/spd/spd_util.c
index d7babbd..cae3974 100644
--- a/src/mainboard/intel/icelake_rvp/spd/spd_util.c
+++ b/src/mainboard/intel/icelake_rvp/spd/spd_util.c
@@ -15,10 +15,10 @@
#include <arch/cpu.h>
#include <intelblocks/mp_init.h>
+#include <intel_mb/spd.h>
#include <stdint.h>
#include <string.h>
-#include "../board_id.h"
#include "spd.h"
enum icl_dimm_type {
@@ -47,13 +47,6 @@
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
}
-static uint8_t get_spd_index(void)
-{
- uint8_t spd_index = (get_board_id() & 0x1F) & 0x7;
-
- return spd_index;
-}
-
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
{
/* DQS CPU<>DRAM map Ch0 */
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 7f1cd89..09b22d5 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -26,6 +26,7 @@
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
+ select MAINBOARD_INTEL_COMMON
select MRC_SETTINGS_PROTECT
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
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