Patrick Georgi submitted this change.
treewide: Capitalize 'CMOS'
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M Documentation/mainboard/msi/ms7707/ms7707.md
M Documentation/releases/coreboot-4.6-relnotes.md
M Makefile.inc
M payloads/libpayload/drivers/options.c
M src/Kconfig
M src/commonlib/include/commonlib/coreboot_tables.h
M src/drivers/pc80/rtc/mc146818rtc.c
M src/drivers/pc80/rtc/option.c
M src/lib/coreboot_table.c
M src/northbridge/intel/gm45/igd.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/x4x/early_init.c
M src/security/vboot/vbnv.h
M src/security/vboot/vbnv_cmos.c
M src/soc/intel/baytrail/acpi/globalnvs.asl
M src/soc/intel/braswell/acpi/globalnvs.asl
M src/soc/intel/broadwell/acpi/globalnvs.asl
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
M src/southbridge/intel/i82371eb/fadt.c
M src/southbridge/intel/i82801gx/acpi/globalnvs.asl
M src/southbridge/intel/i82801ix/acpi/globalnvs.asl
M src/southbridge/intel/i82801jx/acpi/globalnvs.asl
M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
M util/nvramtool/cli/nvramtool.c
M util/nvramtool/layout.c
27 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/Documentation/mainboard/msi/ms7707/ms7707.md b/Documentation/mainboard/msi/ms7707/ms7707.md
index 7894318..c27ff60 100644
--- a/Documentation/mainboard/msi/ms7707/ms7707.md
+++ b/Documentation/mainboard/msi/ms7707/ms7707.md
@@ -75,7 +75,7 @@
to reinitialize (running at full fan speed - don't panic).
* External flashing has been tested with RPi2 without main power connected.
3.3V provided by RPi2. Read more about flashing methods [here](https://doc.coreboot.org/flash_tutorial/index.html).
-* In case of going back to proprietary BIOS create/save cmos settings as early
+* In case of going back to proprietary BIOS create/save CMOS settings as early
as possible (do not leave BIOS on first start without saving settings).
The BIOS might corrupt nvram (not cmos!) and leave the system in a dead state
that needs an external flasher to revive. If stuck, reset the Fintek (see
diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md
index faa3303..4d19ba7f 100644
--- a/Documentation/releases/coreboot-4.6-relnotes.md
+++ b/Documentation/releases/coreboot-4.6-relnotes.md
@@ -164,7 +164,7 @@
* i2c/hid: Add generic I2C HID driver
* i2c/max98927: add i2c driver for Maxim 98927 codec
* i2c/wacom_ts: Add support for WCOM touchscreen device driver
-* pc80/rtc: Check cmos checksum BEFORE reading cmos value
+* pc80/rtc: Check CMOS checksum BEFORE reading CMOS value
* regulator: Add driver for handling GPIO-based fixed regulator
* storage: Add SD/MMC/eMMC driver based upon depthcharge
diff --git a/Makefile.inc b/Makefile.inc
index 1f18726..f172005 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -293,7 +293,7 @@
endef
#######################################################################
-# Parse plaintext cmos defaults into binary format
+# Parse plaintext CMOS defaults into binary format
# arg1: source file
# arg2: binary file name
cbfs-files-processor-nvramtool= \
diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c
index 2b0a42e..0bdb8bc 100644
--- a/payloads/libpayload/drivers/options.c
+++ b/payloads/libpayload/drivers/options.c
@@ -157,7 +157,7 @@
struct cb_cmos_entries *cmos_entry;
int len = name ? strnlen(name, CB_CMOS_MAX_NAME_LENGTH) : 0;
- /* cmos entries are located right after the option table */
+ /* CMOS entries are located right after the option table */
cmos_entry = first_cmos_entry(option_table);
while (cmos_entry) {
if (memcmp((const char*)cmos_entry->name, name, len) == 0)
@@ -186,12 +186,12 @@
struct cb_cmos_enums *first_cmos_enum(struct cb_cmos_option_table *option_table)
{
struct cb_cmos_entries *cmos_entry;
- /* cmos entries are located right after the option table. Skip them */
+ /* CMOS entries are located right after the option table. Skip them */
cmos_entry = (struct cb_cmos_entries *)((unsigned char *)option_table + option_table->header_length);
while (cmos_entry->tag == CB_TAG_OPTION)
cmos_entry = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size);
- /* cmos enums are located after cmos entries. */
+ /* CMOS enums are located after CMOS entries. */
return (struct cb_cmos_enums *)cmos_entry;
}
@@ -237,7 +237,7 @@
{
int len = strnlen(text, CB_CMOS_MAX_TEXT_LENGTH);
- /* cmos enums are located after cmos entries. */
+ /* CMOS enums are located after CMOS entries. */
struct cb_cmos_enums *cmos_enum;
for ( cmos_enum = first_cmos_enum_of_id(option_table, config_id);
cmos_enum;
diff --git a/src/Kconfig b/src/Kconfig
index f75f942..16bc4ab 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -205,7 +205,7 @@
Alignment: 64 bytes
Name Offset Type Size
- cmos_layout.bin 0x0 cmos layout 1159
+ cmos_layout.bin 0x0 CMOS layout 1159
fallback/romstage 0x4c0 stage 339756
fallback/ramstage 0x53440 stage 186664
fallback/payload 0x80dc0 payload 51526
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 6816670..213d821 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -431,15 +431,15 @@
#define MAX_SERIALNO_LENGTH 32
-/* The following structures are for the cmos definitions table */
-/* cmos header record */
+/* The following structures are for the CMOS definitions table */
+/* CMOS header record */
struct cmos_option_table {
uint32_t tag; /* CMOS definitions table type */
uint32_t size; /* size of the entire table */
uint32_t header_length; /* length of header */
};
-/* cmos entry record
+/* CMOS entry record
* This record is variable length. The name field may be
* shorter than CMOS_MAX_NAME_LENGTH. The entry may start
* anywhere in the byte, but can not span bytes unless it
@@ -459,7 +459,7 @@
};
-/* cmos enumerations record
+/* CMOS enumerations record
* This record is variable length. The text field may be
* shorter than CMOS_MAX_TEXT_LENGTH.
*/
@@ -473,8 +473,8 @@
variable length int aligned */
};
-/* cmos defaults record
- * This record contains default settings for the cmos ram.
+/* CMOS defaults record
+ * This record contains default settings for the CMOS ram.
*/
struct cmos_defaults {
uint32_t tag; /* default type */
diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c
index 23f2db3..c197d37 100644
--- a/src/drivers/pc80/rtc/mc146818rtc.c
+++ b/src/drivers/pc80/rtc/mc146818rtc.c
@@ -160,7 +160,7 @@
occurred with !CONFIG_USE_OPTION_TABLE. However, __cmos_init() may
clear vbnv data for other internal reasons. For that, always back up
the vbnv contents and conditionally save them when __cmos_init()
- indicates cmos was cleared. */
+ indicates CMOS was cleared. */
read_vbnv_cmos(vbnv);
if (__cmos_init(invalid))
@@ -204,7 +204,7 @@
year = cmos_read(RTC_CLK_YEAR);
/*
- * TODO: If century is 0xFF, 100% that the cmos is cleared.
+ * TODO: If century is 0xFF, 100% that the CMOS is cleared.
* Other than that, so far rtc_year is the only entry to check
* if the date is valid.
*/
diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c
index ad77669..bb697df 100644
--- a/src/drivers/pc80/rtc/option.c
+++ b/src/drivers/pc80/rtc/option.c
@@ -26,7 +26,7 @@
/*
* This routine returns the value of the requested bits.
- * input bit = bit count from the beginning of the cmos image
+ * input bit = bit count from the beginning of the CMOS image
* length = number of bits to include in the value
* ret = a character pointer to where the value is to be returned
* returns CB_SUCCESS = successful, cb_err code if an error occurred
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index e42cb3b..bd09697 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -505,7 +505,7 @@
* lb_record...
*/
memcpy(rec_dest, option_table, option_table->size);
- /* Create cmos checksum entry in coreboot table */
+ /* Create CMOS checksum entry in coreboot table */
lb_cmos_checksum(head);
} else {
printk(BIOS_ERR,
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index cfd067e..28e93b8 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -153,13 +153,13 @@
if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
sysinfo->ggc = 0x0002;
else {
- /* 4 for 32MB, default if not set in cmos */
+ /* 4 for 32MB, default if not set in CMOS */
u8 gfxsize = 4;
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
2MB GTT + 2MB shadow GTT (0x0b00) else. */
get_option(&gfxsize, "gfx_uma_size");
- /* Handle invalid cmos settings */
+ /* Handle invalid CMOS settings */
/* Only allow settings between 32MB and 352MB */
gfxsize = MIN(MAX(gfxsize, 4), 12);
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 1deca3e..44d2584 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -161,7 +161,7 @@
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
- /* vram size from cmos option */
+ /* vram size from CMOS option */
if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS)
gfxsize = 2; /* 2 for 8MB */
/* make sure no invalid setting is used */
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index c3cd380..8f925f7 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -43,7 +43,7 @@
pci_write_config8(D0F0, DEVEN, BOARD_DEVEN);
- /* vram size from cmos option */
+ /* vram size from CMOS option */
if (get_option(®8, "gfx_uma_size") != CB_SUCCESS)
reg8 = 0; /* 0 for 8MB */
/* make sure no invalid setting is used */
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index 3520b88..fbcfadb 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -56,8 +56,8 @@
/* Enable internal GFX */
pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
- /* Set preallocated IGD size from cmos */
- u8 gfxsize = 6; /* 6 for 64MiB, default if not set in cmos */
+ /* Set preallocated IGD size from CMOS */
+ u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */
get_option(&gfxsize, "gfx_uma_size");
if (gfxsize > 12)
gfxsize = 6;
diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h
index 7d288d5..12b9399 100644
--- a/src/security/vboot/vbnv.h
+++ b/src/security/vboot/vbnv.h
@@ -33,10 +33,10 @@
void vbnv_reset(uint8_t *vbnv_copy);
/* CMOS backend */
-/* Initialize the vbnv cmos backing store. The vbnv_copy pointer is used for
+/* Initialize the vbnv CMOS backing store. The vbnv_copy pointer is used for
optional temporary storage in the init function. */
void vbnv_init_cmos(uint8_t *vbnv_copy);
-/* Return non-zero if cmos power was lost. */
+/* Return non-zero if CMOS power was lost. */
int vbnv_cmos_failed(void);
void read_vbnv_cmos(uint8_t *vbnv_copy);
void save_vbnv_cmos(const uint8_t *vbnv_copy);
diff --git a/src/security/vboot/vbnv_cmos.c b/src/security/vboot/vbnv_cmos.c
index 7758ef6..fe5d6ce 100644
--- a/src/security/vboot/vbnv_cmos.c
+++ b/src/security/vboot/vbnv_cmos.c
@@ -81,13 +81,13 @@
void vbnv_init_cmos(uint8_t *vbnv_copy)
{
- /* If no cmos failure just defer to the normal read path for checking
+ /* If no CMOS failure just defer to the normal read path for checking
vbnv contents' integrity. */
if (!vbnv_cmos_failed())
return;
- /* In the case of cmos failure force the backup. If backup wasn't used
- force the vbnv cmos to be reset. */
+ /* In the case of CMOS failure force the backup. If backup wasn't used
+ force the vbnv CMOS to be reset. */
if (!restore_from_backup(vbnv_copy)) {
vbnv_reset(vbnv_copy);
/* This parallels the vboot_reference implementation. */
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index f33fcf6..703e20f 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -71,8 +71,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 9bd9afc..a67117d 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -73,8 +73,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl
index 9ceeca5..22a22e3 100644
--- a/src/soc/intel/broadwell/acpi/globalnvs.asl
+++ b/src/soc/intel/broadwell/acpi/globalnvs.asl
@@ -63,8 +63,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index b2467f9..e17b260 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -78,8 +78,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index f7652ee..4b54d61 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -138,8 +138,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index cbfb0af..15ab0ee 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -80,7 +80,7 @@
fadt->flush_stride = 0;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
- fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */
+ fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
fadt->mon_alrm = 0x0; /* not supported */
fadt->century = 0x0; /* not supported */
/*
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index 650b07c..23ba6af 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -132,8 +132,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index c1be852..1fc5b74 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -137,8 +137,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index 44aa8e4..c7354a0 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -137,8 +137,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index ba9f850..fddfa70 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -133,8 +133,8 @@
Offset (0xb4),
ASLB, 32, // 0xb4 - IGD OpRegion Base Address
IBTT, 8, // 0xb8 - IGD boot panel device
- IPAT, 8, // 0xb9 - IGD panel type cmos option
- ITVF, 8, // 0xba - IGD TV format cmos option
+ IPAT, 8, // 0xb9 - IGD panel type CMOS option
+ ITVF, 8, // 0xba - IGD TV format CMOS option
ITVM, 8, // 0xbb - IGD TV minor format option
IPSC, 8, // 0xbc - IGD panel scaling
IBLC, 8, // 0xbd - IGD BLC config
diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c
index 9181800..7f3f468 100644
--- a/util/nvramtool/cli/nvramtool.c
+++ b/util/nvramtool/cli/nvramtool.c
@@ -126,7 +126,7 @@
if (!nvramtool_op_modifiers[NVRAMTOOL_MOD_USE_CMOS_FILE].found) {
cmos_default = cbfs_find_file("cmos.default", CBFS_COMPONENT_CMOS_DEFAULT, NULL);
if (cmos_default == NULL) {
- fprintf(stderr, "Need a cmos.default in the CBFS image or separate cmos file (-D).\n");
+ fprintf(stderr, "Need a cmos.default in the CBFS image or separate CMOS file (-D).\n");
exit(1);
}
}
diff --git a/util/nvramtool/layout.c b/util/nvramtool/layout.c
index a340671..884a828 100644
--- a/util/nvramtool/layout.c
+++ b/util/nvramtool/layout.c
@@ -93,7 +93,7 @@
/****************************************************************************
* entries_overlap
*
- * Return 1 if cmos entries 'p' and 'q' overlap. Else return 0.
+ * Return 1 if CMOS entries 'p' and 'q' overlap. Else return 0.
****************************************************************************/
static inline int entries_overlap(const cmos_entry_t * p,
const cmos_entry_t * q)
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