6 comments:
File src/soc/intel/braswell/Makefile.inc:
Patch Set #3, Line 42: ramstage-y += smbus.c
I don't see how this could work in ramstage. The PCI device is
visible to the allocator, which will likely reasign a different
i/o address. Then the static addresses in `smbus.c` wouldn't be
valid any longer.
File src/soc/intel/braswell/include/soc/smbus.h:
nit: single empty line, please
Patch Set #3, Line 24: #define PCH_DEV_SMBUS dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC))
I don't think we actually need this. You don't seem to be using the
SMBus in ramstage and I doubt it's working (see comment in `Makefile.inc`).
File src/soc/intel/braswell/smbus.c:
Patch Set #3, Line 18: #include <device/pci_def.h>
is this needed?
Patch Set #3, Line 22: #include <soc/intel/common/block/smbus/smbuslib.h>
it's really confusing
/* Disable interrupts */
REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0),
/* Clear errors */
REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff),
The sb/common driver should handle these.
To view, visit change 32062. To unsubscribe, or for help writing mail filters, visit settings.