Device (RP09)
{
	Name (_ADR, 0x001D0000)
	OperationRegion(PXCS,SystemMemory,0xC00E8000,0xC80)
  	Field(PXCS,AnyAcc, NoLock, Preserve)
  	{
		Offset(0),
		VDID, 32,
		Offset(0x50), // LCTL - Link Control Register
		L0SE, 1,      // 0, L0s Entry Enabled
		Offset(0x52), // LSTS - Link Status Register
		, 13,
		LASX, 1,      // 0, Link Active Status
		Offset(0x5A), // SLSTS[7:0] - Slot Status Register
		, 3,
		PDCX, 1,      // 3, Presence Detect Changed
		, 2,
		PDSX, 1,      // 6, Presence Detect State
		, 1,
		Offset(0x60), // RSTS - Root Status Register
		, 16,
		PSPX, 1,      // 16,  PME Status
		Offset(R_PCH_PCIE_CFG_MPC), // 0xD8, MPC - Miscellaneous Port Configuration Register
		, 30,
		HPEX, 1,      // 30,  Hot Plug SCI Enable
		PMEX, 1,      // 31,  Power Management SCI Enable
		Offset(R_PCH_PCIE_CFG_SPR),    // 0xE0, SPR - Scratch Pad Register
		, 7,
		NCB7, 1,                   // Non-Sticky Scratch Pad Bit (NSCB)[7]
		Offset(R_PCH_PCIE_CFG_RPPGEN), // 0xE2, RPPGEN - Root Port Power Gating Enable
		, 2,
		L23E, 1,      // 2,   L23_Rdy Entry Request (L23ER)
		L23R, 1,       // 3,   L23_Rdy to Detect Transition (L23R2DT)
		Offset(0xF4), // BLKPLLEN
		, 10,
		BPLL, 1,
		Offset(0x338), // BLKDQDA
		, 26,
		BDQA, 1,
		Offset(R_PCH_PCIE_CFG_PCIEPMECTL), // 0x420, PCIEPMECTL (PCIe PM Extension Control)
		, 30,
		DPGE, 1,       // PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane Power Gating Enable (DLSULPPGE):
		}

	/* L23D is called from _ON to get PCIe link back to Active State */
  	Method (L23D, 0, Serialized) {
		Store(0x21, PST0)
    		If(LNotEqual(NCB7,0x1)) {
			Store(0x22, PST0)
			Return()
    		}
    		Store(1, L23R)
    		Store(0, Local0)
    		/* Wait for transition to Detect */
    		While(L23R) {
      			If(Lgreater(Local0, 20))
      			{
				Store(0x23, PST0)
        			Break
      			}
      			Sleep(16)
      			Increment(Local0)
    		}
    		Store(0,NCB7)
		/* Once in Detect, wait up to 124 ms for Link Active (typically happens in under 70ms) */
		Store(0, Local0)
    		While(LEqual(LASX,0)) {
      			If(Lgreater(Local0, 20))
			{
				Store(0x24, PST0)
				Break
			}
			//CDLY(10000*60)
			Increment(Local0)
		}
  	}

	/* DL23 method is called from _OFF to put PCIe link into L2/L3 State */
	Method (DL23, 0, Serialized) {
		Store(0x11, PST0)
		Store(1, L23E)
		Sleep(16)
		Store(0, Local0)
		While(L23E) {
			Store(0x12, PST0)
			If(Lgreater(Local0, 4)) {
				Store(0x13, PST0)
				Break
			}
			Sleep(16)
			Increment(Local0)
		}
  	Store (1, NCB7)
	}

	PowerResource (PR09, 0x00, 0x0000)
	{
		Method (_ON, 0, Serialized)  /* Power On */
		{
			/* _ON entry: Post codes: 0x90 */
			Store(0x90, PST0)

			/* Set Power Pin High */
			STXS(SSD_POWER_GPIO)

			/* Unmask PCIe Source Clock */
			ShiftLeft(0x1, PCIERP8_SRCCLKINDEX, Local0) // 0x1 left shift by clock number (3)
                	ShiftLeft(0x1, PCIERP8_SRCCLKINDEX, Local1) // Clock Enable/Disable 1/0 -> left shift by clock number
                	ShiftLeft(0x1, 8, Local2) // Local 0 -> 0x1 left shifted by Root Port Index Starting from 0
                	ShiftLeft(0x1, 8, Local3) // Local 1 -> 0x1 (Unmask) left shifted by Root Port Index Starting from 0
                	IPCS(0xAC, 0, 16, Local0, Local1, Local2, Local3)

			/* De-assert reset pin */
			STXS(SSD_RESET_GPIO)

			/* Trigger L2/L3 ready exit flow in rootport - transition link to Detect */
			\_SB.PCI0.RP09.L23D()
		}
		Method (_OFF, 0, Serialized)  /* Power Off */
		{
			/* _OFF entry: Post Codes: 0x93 */
			Store(0x93, PST0)

			/* Trigger L2/L3 ready entry flow in rootport */
			\_SB.PCI0.RP09.DL23()

			/* Assert reset pin */
			CTXS(SSD_RESET_GPIO)

			/* Mask PCIe Source Clock */
	 		ShiftLeft(0x1, PCIERP8_SRCCLKINDEX, Local0) // 0x1 left shift by clock number (3)
			ShiftLeft(0x0, PCIERP8_SRCCLKINDEX, Local1) // Clock Enable/Disable 1/0 -> left shift by clock number
			ShiftLeft(0x1, 8, Local2) // Local 0 -> 0x1 left shifted by Root Port Index Starting from 0
			ShiftLeft(0x0, 8, Local3) // Local 1 -> 0x0 (Mask) left shifted by Root Port Index Starting from 0
			IPCS(0xAC, 0, 16, Local0, Local1, Local2, Local3)

			/* Power off the power pin */
			CTXS(SSD_POWER_GPIO)
		}
		Method (_STA, 0, NotSerialized)  /* _STA: Status */
		{
			Store(0x88, PST0)
			If(GTXS(SSD_RESET_GPIO)) {
				Store(0x1, PST0)
				Return (1)
			} Else {
				Store(0x0, PST0)
				Return (0)
			}
		}
	}

	Name (_PR0, Package (0x01)  /* _PR0: Power Resources for D0 */
	{
		PR09
	})
	Name (_PR3, Package (0x01)  /* _PR3: Power Resources for D3hot */
	{
		PR09
	})

	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
	Field (RPCS, AnyAcc, NoLock, Preserve)
	{
		, 24,
		RPPN, 8,	/* Root Port Number */
	}

	Method (_PRT)
	{
		Return (IRQM (RPPN))
	}

	Device (PXSX)
	{
		Name (_ADR, 0x00000000)
		Name (_S0W, 4)
		Method (_DSD, 0) {
        	Return (
          		Package () {
            			ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
            			// Enable D3 Support for NVMe Storage
            			Package () {
              				Package (2) {"StorageD3Enable",1}  // 1 - Enable; 0 - Disable
            			}
          		}
        		)
      		}
	}
}