1 comment:
File src/drivers/mrc_cache/mrc_cache.c:
/* Read Write Protect GPIO if available */
wp_gpio = get_write_protect_state();
One problem that I can think of here is: when SW WP is enabled, but HW WP isn't. In such cases, I believe the firmware updater(https://chromium.git.corp.google.com/chromiumos/platform/vboot_reference/+/5059062dd352e3864fb68f8a061e87bd7055d12a/futility/updater.c#623) considers that write protection is disabled because flashrom can temporarily set status registers to 0 to allow RO+RW update.
But, if coreboot configures PRR to protect MRC cache based on SW WP only, then RO+RW update would not be able to write to MRC cache, thus resulting in firmware update failure.
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