Felix Held submitted this change.
soc/amd/*/romstage: factor out FSP-M call
Move the call into the FSP code to a file in the common AMD FSP code to
isolate the FSP-specific parts of the code and a preparation to make the
romstage of all non-CAR AMD SoCs common. Without isolating the call into
the FSP-M code, building the common romstage would fail for genoa_poc
due to fsp/api.h not being in the include path.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I30cf1bee2ec1a507dc8e61eaf44067663e2505ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
---
M src/soc/amd/cezanne/romstage.c
A src/soc/amd/common/block/include/amdblocks/fsp.h
M src/soc/amd/common/fsp/Makefile.inc
A src/soc/amd/common/fsp/fsp_romstage.c
M src/soc/amd/glinda/romstage.c
M src/soc/amd/mendocino/romstage.c
M src/soc/amd/phoenix/romstage.c
M src/soc/amd/picasso/romstage.c
8 files changed, 29 insertions(+), 15 deletions(-)
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 63a6b07..6b84728 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -18,7 +17,7 @@
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/common/block/include/amdblocks/fsp.h b/src/soc/amd/common/block/include/amdblocks/fsp.h
new file mode 100644
index 0000000..a7b664f
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/fsp.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_FSP_H
+#define AMD_BLOCK_FSP_H
+
+void amd_fsp_early_init(void);
+
+#endif /* AMD_BLOCK_FSP_H */
diff --git a/src/soc/amd/common/fsp/Makefile.inc b/src/soc/amd/common/fsp/Makefile.inc
index 14f1f85..2517f0c 100644
--- a/src/soc/amd/common/fsp/Makefile.inc
+++ b/src/soc/amd/common/fsp/Makefile.inc
@@ -2,6 +2,7 @@
ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
romstage-y += fsp_memmap.c
romstage-y += fsp_reset.c
+romstage-y += fsp_romstage.c
romstage-y += fsp_validate.c
ramstage-y += fsp_graphics.c
ramstage-y += fsp_memmap.c
diff --git a/src/soc/amd/common/fsp/fsp_romstage.c b/src/soc/amd/common/fsp/fsp_romstage.c
new file mode 100644
index 0000000..26778f1
--- /dev/null
+++ b/src/soc/amd/common/fsp/fsp_romstage.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <amdblocks/fsp.h>
+#include <fsp/api.h>
+
+void amd_fsp_early_init(void)
+{
+ fsp_memory_init(acpi_is_wakeup_s3());
+}
diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c
index 63a6b07..6b84728 100644
--- a/src/soc/amd/glinda/romstage.c
+++ b/src/soc/amd/glinda/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -18,7 +17,7 @@
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c
index 83a8bf9..f1ee595 100644
--- a/src/soc/amd/mendocino/romstage.c
+++ b/src/soc/amd/mendocino/romstage.c
@@ -1,14 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <amdblocks/stb.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -22,7 +21,7 @@
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/phoenix/romstage.c b/src/soc/amd/phoenix/romstage.c
index 63a6b07..6b84728 100644
--- a/src/soc/amd/phoenix/romstage.c
+++ b/src/soc/amd/phoenix/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
@@ -18,7 +17,7 @@
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index c43b249..5159061 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -1,13 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
+#include <amdblocks/fsp.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <amdblocks/post_codes.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/cpu.h>
-#include <fsp/api.h>
#include <program_loading.h>
#include <romstage_common.h>
#include <types.h>
@@ -19,7 +18,7 @@
/* Snapshot chipset state prior to any FSP call. */
fill_chipset_state();
- fsp_memory_init(acpi_is_wakeup_s3());
+ amd_fsp_early_init();
memmap_stash_early_dram_usage();
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