Subrata Banik has uploaded this change for review.

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soc/intel/mtl: Skip RW CBFS ucode update if RO is locked

This patch optimizes boot time by avoiding redundant microcode updates
from RW CBFS when the RO descriptor is locked, indicating a fixed RO
image.

1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
(~60ms, core-dependent).
3. The kernel can still load microcode updates without affecting
AP FW boot time.

ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.

BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS
microcode loading when RO is locked.

Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a
Signed-off-by: Subrata Banik <subratabanik@google.com>
---
M src/soc/intel/meteorlake/cpu.c
1 file changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/80567/1
diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c
index 54217ea5..e990ae3 100644
--- a/src/soc/intel/meteorlake/cpu.c
+++ b/src/soc/intel/meteorlake/cpu.c
@@ -4,6 +4,7 @@
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/common/common.h>
+#include <cpu/intel/microcode.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/lapic.h>
@@ -214,3 +215,24 @@
/* Thermal throttle activation offset */
configure_tcc_thermal_target();
}
+
+int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
+{
+ if (!CONFIG(CHROMEOS))
+ return 0;
+ /*
+ * Locked RO Descriptor Implications:
+ *
+ * - A locked descriptor signals the RO binary is fixed; the FIT will load the
+ * RO's microcode during system reset.
+ * - Attempts to load newer microcode from the RW CBFS will cause a boot-time
+ * delay (~60ms, core-dependent), as the microcode must be reloaded on BSP+APs.
+ * - The kernel can load microcode updates without impacting AP FW boot time.
+ * - Skipping RW CBFS microcode loading is low-risk when the RO is locked,
+ * prioritizing fast boot times.
+ */
+ if (CONFIG(LOCK_MANAGEMENT_ENGINE) && current_patch_id)
+ return 1;
+
+ return 0;
+}

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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ia859809970406fca3fa14e6fa8e766ab16d94c8a
Gerrit-Change-Number: 80567
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subratabanik@google.com>
Gerrit-MessageType: newchange