Martin Roth has uploaded this change for review.
drivers/intel/fsp2_0: Add mb hooks before & after FSP calls
There are currently various callbacks and hooks for chipsets and
mainboards in various places around the FSP calls, but I need some
mainboard hooks immediately before and after the FSP calls.
This allows for GPIO initialization before the calls as required and
easy analysis and updates of register changes within the FSP.
BUG=None
TEST=Build & Boot guybrush with following patches
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8dc6eb95fa8a1114234cfd7467507992c25669f1
---
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
3 files changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/52866/1
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 8561600..3450050 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -71,6 +71,15 @@
struct mma_config_param *mma_cfg);
/*
+ * Weak functions before and after FSP-M and FSP-S calls for use by mainboards.
+ * These can save and restore registers, print values, or do other initialization.
+ */
+void mb_pre_fspm_init(void);
+void mb_post_fspm_init(void);
+void mb_pre_fsps_init(void);
+void mb_post_fsps_init(void);
+
+/*
* As per FSP integration guide:
* If bootloader needs to take control of APs back, a full AP re-initialization is
* required after FSP-S is completed and control has been transferred back to bootloader
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index bbc26bc..c5d560a 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -195,6 +195,14 @@
return 0;
}
+__weak void mb_pre_fspm_init(void)
+{
+}
+
+__weak void mb_post_fspm_init(void)
+{
+}
+
/*
* Allow SoC and/or mainboard to bump the revision of the FSP setting
* number. The FSP spec uses the low 8 bits as the build number. Take over
@@ -386,9 +394,12 @@
die("FSPM XIP base does not match: %p vs %p\n",
(void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog));
+ mb_pre_fspm_init();
timestamp_add_now(TS_BEFORE_INITRAM);
do_fsp_memory_init(&context, s3wake);
timestamp_add_now(TS_AFTER_INITRAM);
+ mb_post_fspm_init();
+
}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 53c9626..707a380 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -34,6 +34,14 @@
return 1;
}
+__weak void mb_pre_fsps_init(void)
+{
+}
+
+__weak void mb_post_fsps_init(void)
+{
+}
+
/* FSP Specification < 2.2 has only 1 stage like FspSiliconInit. FSP specification >= 2.2
* has multiple stages as below.
*/
@@ -221,7 +229,10 @@
void fsp_silicon_init(void)
{
fsps_load();
+
+ mb_pre_fsps_init();
do_silicon_init(&fsps_hdr);
+ mb_post_fsps_init();
}
__weak void soc_load_logo(FSPS_UPD *supd) { }
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