Sridhar Siricilla has uploaded this change for review.
soc/intel/common/block/cse: Move me_read_config32() to common code
me_read_config32() is defined in multiple places, move it to common
location. Also, move HFSTS macros specific to CSE PCI config header
into common header file.
Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
---
M src/soc/intel/apollolake/cse.c
M src/soc/intel/cannonlake/me.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/include/intelblocks/cse.h
M src/soc/intel/skylake/include/soc/me.h
M src/soc/intel/skylake/me.c
6 files changed, 51 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35225/1
diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c
index 82226ec..32e9222 100644
--- a/src/soc/intel/apollolake/cse.c
+++ b/src/soc/intel/apollolake/cse.c
@@ -28,12 +28,6 @@
#include <device/pci_ops.h>
#include <stdint.h>
-#define PCI_ME_HFSTS1 0x40
-#define PCI_ME_HFSTS2 0x48
-#define PCI_ME_HFSTS3 0x60
-#define PCI_ME_HFSTS4 0x64
-#define PCI_ME_HFSTS5 0x68
-#define PCI_ME_HFSTS6 0x6c
#define MKHI_GROUP_ID_MCA 0x0a
#define READ_FILE 0x02
@@ -49,6 +43,8 @@
#define FUSE_LOCK_FILE "/fpf/intel/SocCfgLock"
+#define dump_status(index, hfs_reg) me_read_config32(hfs_reg)
+
/* Status values are made in such a way erase is not needed */
static enum fuse_flash_state {
FUSE_FLASH_FUSED = 0xfc,
@@ -186,15 +182,6 @@
printk(BIOS_CRIT, "failed to save FPF state\n");
}
-static uint32_t dump_status(int index, int reg_addr)
-{
- uint32_t reg = pci_read_config32(PCH_DEV_CSE, reg_addr);
-
- printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg);
-
- return reg;
-}
-
static void dump_cse_version(void *unused)
{
int res;
diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c
index b8b4245d..dab909b 100644
--- a/src/soc/intel/cannonlake/me.c
+++ b/src/soc/intel/cannonlake/me.c
@@ -32,16 +32,6 @@
ME_WSTATE_NORMAL = 0x05,
};
-/* HFSTS register offsets in PCI config space */
-enum {
- PCI_ME_HFSTS1 = 0x40,
- PCI_ME_HFSTS2 = 0x48,
- PCI_ME_HFSTS3 = 0x60,
- PCI_ME_HFSTS4 = 0x64,
- PCI_ME_HFSTS5 = 0x68,
- PCI_ME_HFSTS6 = 0x6C,
-};
-
/* Host Firmware Status Register 1 */
union hfsts1 {
uint32_t raw;
@@ -155,11 +145,6 @@
} __packed fields;
};
-static uint32_t me_read_config32(int offset)
-{
- return pci_read_config32(PCH_DEV_CSE, offset);
-}
-
/*
* From reading the documentation, this should work for both WHL and CML
* platforms. Also, calling this function from dump_me_status() does not
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 97989f7..69cb273 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -507,6 +507,39 @@
return 0;
}
+uint32_t me_read_config32(int offset)
+{
+ uint32_t reg;
+
+ reg = pci_read_config32(PCH_DEV_CSE, offset);
+
+ if (!CONFIG(CONSOLE_SERIAL))
+ {
+ uint8_t index;
+
+ if( offset == PCI_ME_HFSTS1)
+ index = 1;
+ else if (offset == PCI_ME_HFSTS2)
+ index = 2;
+ else if (offset == PCI_ME_HFSTS3)
+ index = 3;
+ else if (offset == PCI_ME_HFSTS4)
+ index = 4;
+ else if (offset == PCI_ME_HFSTS5)
+ index = 5;
+ else if (offset == PCI_ME_HFSTS6)
+ index = 6;
+ else
+ index = 0;
+
+ if (index != 0)
+ printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg);
+ else
+ printk(BIOS_DEBUG, "CSE [0x%x]=0x%08x\n", offset, reg);
+ }
+ return reg;
+}
+
#if ENV_RAMSTAGE
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 371a781..9409ce5 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -53,7 +53,23 @@
*/
int heci_reset(void);
+/*
+ * Reads config value from a specified offset in the HECI Configuration
+ *
+ */
+uint32_t me_read_config32(int offset);
+
#define BIOS_HOST_ADDR 0x00
#define HECI_MKHI_ADDR 0x07
+/* HFSTS register offsets in PCI config space */
+enum {
+ PCI_ME_HFSTS1 = 0x40,
+ PCI_ME_HFSTS2 = 0x48,
+ PCI_ME_HFSTS3 = 0x60,
+ PCI_ME_HFSTS4 = 0x64,
+ PCI_ME_HFSTS5 = 0x68,
+ PCI_ME_HFSTS6 = 0x6C,
+};
+
#endif // SOC_INTEL_COMMON_MSR_H
diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h
index 5a9acd5..fbe5033 100644
--- a/src/soc/intel/skylake/include/soc/me.h
+++ b/src/soc/intel/skylake/include/soc/me.h
@@ -21,7 +21,6 @@
/*
* Management Engine PCI registers
*/
-#define PCI_ME_HFSTS1 0x40
#define ME_HFS_CWS_RESET 0
#define ME_HFS_CWS_INIT 1
#define ME_HFS_CWS_REC 2
@@ -169,7 +168,6 @@
} __packed fields;
};
-#define PCI_ME_HFSTS3 0x60
#define ME_HFS3_FW_SKU_CONSUMER 0x2
#define ME_HFS3_FW_SKU_CORPORATE 0x3
@@ -186,9 +184,6 @@
} __packed fields;
};
-#define PCI_ME_HFSTS4 0x64
-#define PCI_ME_HFSTS5 0x68
-#define PCI_ME_HFSTS6 0x6c
#define ME_HFS6_FPF_NOT_COMMITTED 0x0
#define ME_HFS6_FPF_ERROR 0x2
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index f7aa584..e8d75e3 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -26,10 +26,6 @@
#include <stdlib.h>
#include <string.h>
-static inline u32 me_read_config32(int offset)
-{
- return pci_read_config32(PCH_DEV_CSE, offset);
-}
/* HFSTS1[3:0] Current Working State Values */
static const char *const me_cws_values[] = {
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