Elyes Haouas has uploaded this change for review.

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mainboard: Use write{64,32,16,8}p and read{64,32,16,8}p

Change-Id: I0a4ecd9566e9b715c1209bee26a30f3281548845
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
---
M src/mainboard/emulation/qemu-riscv/clint.c
M src/mainboard/emulation/spike-riscv/clint.c
M src/mainboard/google/mistral/mainboard.c
M src/mainboard/protectli/vault_cml/mainboard.c
M src/mainboard/siemens/fa_ehl/romstage_fsp_params.c
M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
6 files changed, 7 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/80195/1
diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c
index 10827fa..3436568 100644
--- a/src/mainboard/emulation/qemu-riscv/clint.c
+++ b/src/mainboard/emulation/qemu-riscv/clint.c
@@ -14,5 +14,5 @@

void set_msip(int hartid, int val)
{
- write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val);
+ write32p((QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val);
}
diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c
index 4d45bce..f510e0b 100644
--- a/src/mainboard/emulation/spike-riscv/clint.c
+++ b/src/mainboard/emulation/spike-riscv/clint.c
@@ -15,5 +15,5 @@

void set_msip(int hartid, int val)
{
- write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val);
+ write32p((SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val);
}
diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c
index e45ff8f..0dd1360 100644
--- a/src/mainboard/google/mistral/mainboard.c
+++ b/src/mainboard/google/mistral/mainboard.c
@@ -22,7 +22,7 @@
static void configure_sdhci(void)
{
/* Program eMMC drive strength to 16/10/10 mA */
- write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4);
+ write32p(SDC1_TLMM_CFG_ADDR, 0x9FE4);
}

static void mainboard_init(struct device *dev)
diff --git a/src/mainboard/protectli/vault_cml/mainboard.c b/src/mainboard/protectli/vault_cml/mainboard.c
index 1e06fc5..515cb70 100644
--- a/src/mainboard/protectli/vault_cml/mainboard.c
+++ b/src/mainboard/protectli/vault_cml/mainboard.c
@@ -51,14 +51,14 @@
static bool is_descriptor_writeable(uint8_t *desc)
{
/* Check flash has valid signature */
- if (read32((void *)(desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) {
+ if (read32p((desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) {
printk(BIOS_ERR, "Flash Descriptor is not valid\n");
printk(BIOS_ERR, "Descriptor needs to be fixed to ensure proper operation\n");
return false;
}

/* Check host has write access to the Descriptor Region */
- if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) {
+ if (!((read32p((desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) {
printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n");
return false;
}
diff --git a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c
index 506bcc6..7337e27 100644
--- a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c
@@ -22,7 +22,7 @@
memset(spd_data, 0, sizeof(spd_data));
if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
(hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&
- (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) {
+ (ddr_crc16(spd_data, 126) == read16p(&spd_data[126]))) {
spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data;
spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE;
spd_info.read_type = READ_SPD_MEMPTR;
diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
index d386d75..b74a60e 100644
--- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
+++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c
@@ -26,7 +26,7 @@
memset(spd_data, 0, sizeof(spd_data));
if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) &&
(hwilib_get_field(SPD, spd_data, 0x80) == 0x80) &&
- (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) {
+ (ddr_crc16(spd_data, 126) == read16p(&spd_data[126]))) {
spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data;
spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE;
spd_info.read_type = READ_SPD_MEMPTR;

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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I0a4ecd9566e9b715c1209bee26a30f3281548845
Gerrit-Change-Number: 80195
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes Haouas <ehaouas@noos.fr>
Gerrit-MessageType: newchange